Memory cell having negative differential resistance devices

• US 5,883,829 A
• Filed: 06/27/1997
• Issued: 03/16/1999
• Est. Priority Date: 06/27/1997
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: van der Wagt, Jan P.
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US08/883,737
• Time in Patent Office: 627 Days
• Field of Search: 257/377, 257/351, 257/197, 326/135, 365/174, 365/775
• US Class Current: 365/159
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 11/39 using thyristors or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 2211/5614 Multilevel memory cell comprising negative resistance, quantum tunneling or resonance tunneling elements
• CPC Class Codes: G11C 5/142 Contactless power supplies, e.g. RF, induction, or IR

Abstract

A memory system is organized as a matrix including a memory cell at each intersection of a bit line with write and read word lines Each memory cell comprises a first FET 20 having its gate coupled to a write word line and its drain coupled to a bit line, a second FET 22 having its source coupled to the bit line and its drain coupled to a read word line, and first and second negative resistance devices 24,26 coupled in series between a supply voltage and a substrate voltage, the common point SN of the series-connected negative resistance devices being coupled to the source of the first PET and to the gate of the second FET. Preferably, the first FET 20 is a p-channel device, the second FET 22 is an n-channel device, and the first and second negative resistance devices 24,26 are RTDs. In a second embodiment, a memory system has a memory cell at each intersection of a bit line with a word line. The memory cell comprises an FET having its gate coupled to a word line and one of its drain and source electrodes coupled to a bit line, first and second negative resistance devices 44,46 coupled in series between a supply voltage and a substrate voltage, the common point SN of the series-connected negative resistance devices being coupled to the other of the drain and source electrodes, and a capacitance 48 coupled between the common point of the series-connected negative resistance devices.

Claims

1. In a memory system organized as a matrix including a memory cell at each intersection of a bit line with write and read word lines, said memory cell comprising:

a first field effect transistor (FET) having its gate electrode coupled to a write word line and its drain electrode coupled to a bit line;

a second FET having its source electrode coupled to said bit line and its drain electrode coupled to a read word line; and

first and second negative resistance devices coupled in series between a supply voltage and a substrate voltage, the common point of said series-connected negative resistance devices being coupled to the source electrode of said first FET and to the gate electrode of said second FET.

2. The memory cell in accordance with claim 1 wherein said first FET is a p-channel FET.

3. The memory cell in accordance with claim 1 wherein said second FET is an n-channel FET.

4. The memory cell in accordance with claim 1 wherein said first and second negative resistance devices are resonant tunneling diodes (RTDs).