Pattern data compression and decompression for semiconductor test system

• US 5,883,906 A
• Filed: 08/15/1997
• Issued: 03/16/1999
• Est. Priority Date: 08/15/1997
• Status: Expired due to Fees

• Current Assignee: Advantest Corporation
• Original Assignee: Advantest Corporation
• Inventors: Chen, Leon Lee, Turnquist, James Alan
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Iqbal, Nadeem
• Application Number:
  US08/911,929
• Time in Patent Office: 578 Days
• Field of Search: 371/27.1, 371/22.33, 371/22.6, 371/28, 371/37.6, 395/878, 395/880, 395/416, 395/421.07, 395/421.08, 395/421.11, 395/183.08, 364/488, 364/490, 364/550, 364/718
• US Class Current: 714/738
• CPC Class Codes: G01R 31/31908 Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns

Abstract

A compression and decompression apparatus to be used for transferring test pattern data from a storage device of a host computer to a pattern memory in a semiconductor test system for testing a semiconductor device to decrease the time required for the data transfer. The compression and decompression apparatus includes: a compression means for classifying vector data in the test pattern data into a first group to be compressed to a short code and a second group not to be compressed, and for producing a look-up table showing relationship between the short code and the vector data in the first group; a compressed test pattern file storing compressed test pattern including the short code, data vector in the second group and the look-up table; and a hardware decompression circuit provided in the semiconductor test system or proximity thereto for decompressing the compressed test pattern based on the short code and the relationship shown in the look-up table and for sending decompressed test pattern to the pattern memory in the semiconductor test system.

Claims

1. A compression and decompression method to be used for transferring test pattern data from a storage device of a host computer to a pattern memory in a semiconductor test system for testing a semiconductor device, comprising the following steps of:

extracting vector data from a test pattern file in said storage device;

classifying said vector data into three groups, a first group of which has a higher frequency of data repetition, a second group has an intermediate frequency of data repetition and a third group has a lower frequency of data repetition than that of said first or second group;

converting said vector data in said first and second groups to a short code and a long code, respectively, indicating an order of said data repetition rate, and specifying said vector data in said third group by an escape code and attaching said vector data in said third group to said escape code;

forming a translation table showing the relationship between said short code and said vector data in said first group and between said long code and said vector data in said second group;

merging said short code, said long code and said escape code attached by said vector data in said third group with non-vector data from said storage device to form a compressed test pattern file;

receiving said compressed test pattern by a decompression means and detecting said short code, said long code and said escape code in said compressed test pattern;

translating said short code and long code to corresponding vector data in said first and second groups based on said relationship shown in said translation table by said decompression means; and

sending said vector data in said first and second groups translated by said decompression means and said vector data in said third group to said pattern memory in said semiconductor test system.

2. A compression and decompression method as defined in claim 1, wherein each of said vector data in said pattern file is configured by eight bytes (64 bits) and said short code is configured one byte and said long code is configured by two bytes.

3. A compression and decompression method as defined in claim 1, wherein each of said vector data in said pattern file is configured by eight bytes (64 bits) and said short code and is configured one byte and said long code is configured by two bytes and said escape code is configured by one byte which is attached by the eight byte vector data in said third group.

4. A compression and decompression method as defined in claim 1, wherein each of said vector data in said pattern file is configured by eight bytes (64 bits) and said short code represents 127 most frequently repeated vector data in said first group while said long code represents the next 1920 most repeated vector data in said second group.

5. A compression and decompression apparatus to be used for transferring test pattern data from a storage device of a host computer to a pattern memory in a semiconductor test system for testing a semiconductor device, comprising:

a compression means for classifying vector data in said test pattern data into a first group to be compressed to a short code and a second group not to be compressed, and for producing a look-up table showing relationship between said short code and said vector data in said first group;

a compressed test pattern file storing compressed test pattern including said short code, data vector in said second group and said look-up table; and

a hardware decompression circuit provided in said semiconductor test system or proximity thereto for decompressing said compressed test pattern based on said short code and said relationship shown in said look-up table and for sending decompressed test pattern to said pattern memory in said semiconductor test system.

6. A compression and decompression apparatus as defined in claim 5, wherein said compression means classify said vector data based on frequencies of data repetition in said test pattern data, and said compressed pattern file is merged by said compressed test pattern and non-vector data in said test pattern data.

7. A compression and decompression apparatus as defined in claim 5, said hardware decompression circuit comprising:

a control logic for controlling an overall decompression operation;

a latch for receiving said compressed test pattern under the control of said control logic;

a memory for storing said look-up table transferred from said compressed test pattern file to read the test pattern data based on said short code; and

a selector for selecting either output data of said memory or output data of said latch under the control of said control logic.

8. A compression and decompression apparatus as defined in claim 7, said hardware decompression circuit further comprising an AND circuit which is controlled by said control logic for providing a second byte in said short code to said memory.

9. A compression and decompression apparatus as defined in claim 5, wherein each of said vector data in said test pattern data is configured by eight bytes (64 bits) and said short code is configured either one byte or two bytes.

10. A compression and decompression apparatus as defined in claim 5, wherein each of said vector data in said test pattern data is configured by eight bytes (64 bits) and said short code is configured either one byte or two bytes, and said vector data in said second group is provided with an escape code configured by one byte.

11. A compression and decompression apparatus to be used for transferring test pattern data from a storage device of a host computer to a pattern memory in a semiconductor test system for testing a semiconductor device, comprising:

means for extracting vector data from a test pattern file in said storage device;

means for classifying said vector data into three groups, a first group of which has a higher frequency of data repetition, a second group has an intermediate frequency of data repetition and a third group has a lower frequency of data repetition than that of said first or second group;

means for converting said vector data in said first and second groups to a short code and a long code, respectively, indicating an order of said data repetition rate, and specifying said vector data in said third group by an escape code and attaching said vector data in said third group to said escape code;

means for forming a translation table showing the relationship between said short code and said vector data in said first group and between said long code and said vector data in said second group;

means for merging said short code, said long code and said escape code attached by said vector data in said third group with non-vector data from said storage device to form a compressed test pattern file;

a control logic provided in said semiconductor test system or proximate thereto for controlling an overall decompression operation;

a latch for receiving said compressed test pattern under the control of said control logic;

a memory for storing said translation table transferred from said compressed test pattern file to read the test pattern data based on said short and long codes; and

a selector for selecting either output data of said memory or output data of said latch under the control of said control logic.

12. A compression and decompression apparatus as defined in claim 11, further comprising an AND circuit which is controlled by said control logic for providing a second byte in said long code to said memory.

13. A compression and decompression apparatus as defined in claim 11, wherein each of said vector data in said pattern file is configured by eight bytes (64 bits) and said short code is configured one byte and said long code is configured by two bytes.

14. A compression and decompression apparatus as defined in claim 11, wherein each of said vector data in said pattern file is configured by eight bytes (64 bits) and said short code and is configured one byte and said long code is configured by two bytes and said escape code is configured by one byte which is attached by the eight byte vector data in said third group.

15. A compression and decompression method as defined in claim 11, wherein each of said vector data in said pattern file is configured by eight bytes (64 bits) and said short code represents 127 most frequently repeated vector data while said long code represents the next 1920 most repeated vector data in said pattern file.