High speed semiconductor laser driver circuits

• US 5,883,910 A
• Filed: 07/03/1997
• Issued: 03/16/1999
• Est. Priority Date: 07/03/1997
• Status: Expired due to Fees

• Current Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Original Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Inventors: Link, Garry N.
• Primary Examiner(s): Sanghavi, Hemang
• Application Number:
  US08/888,026
• Time in Patent Office: 621 Days
• Field of Search: 372/26, 372/29, 372/34, 372/38
• US Class Current: 372/38.07
• CPC Class Codes: H01S 5/042 Electrical excitation ; Circuits therefor monolithically integrated laser drive components H01S5/0261

Abstract

A semiconductor laser driver circuit that provides single supply operation over a wide supply voltage range (e.g., 3 V to 5.5 V), is capable of high speed data transmission, and is programmable over a wide laser modulation current range (such as 5 mA to 60 mA). The circuit includes temperature sensitive circuits to adjust for changes in Vbe over the operating temperature range, and to adjust a bias current to maintain transistor g_m in the presence of temperature changes. Also included is an adaptive drive feature to accommodate different laser drive currents. Details of these and other features are disclosed.

Claims

1. A circuit for providing a semiconductor laser drive current comprising:

a laser drive circuit having first and second input lines forming a differential input for providing the laser drive current when the voltage on the first line is higher than the voltage on the second line and for not providing the laser drive current when the voltage on the second line is higher than the voltage on the first line; and

,

an active differential pull-up/pull-down circuit responsive to differential signals for actively pulling the voltage on the first input line of the laser drive circuit up and actively pulling the voltage on the second input line of the laser drive circuit down when the laser drive current is to be provided, and pulling the voltage on the first input line of the laser drive circuit down and pulling the voltage on the second input line of the laser drive circuit up when the laser drive current is not to be provided.

2. The laser drive circuit of claim 1 further comprised of first and second current sources coupled to the first and second input lines of the laser drive circuit, respectively.

3. The laser drive circuit of claim 1 wherein the laser drive circuit is an AC coupled circuit with inductive pull-up.

4. The laser drive circuit of claim 3 further comprised of a first level shift circuit coupled to the active differential pull-up/pull-down circuit to provide the differential signals thereto to allow operation of the laser drive circuit with a range of power supply voltages.

5. The laser drive circuit of claim 3 further comprised of a second level shift circuit coupled to the active differential pull-up/pull-down circuit to provide differential signals thereto having a different common mode voltage than differential input signals provided to the second level shift circuit.

6. In a semiconductor laser driver circuit, the improvement comprising:

first and second power supply connections;

first, second, third and fourth transistors, each having an emitter, a base and a collector;

the first and second transistors having their emitters coupled together and through a first current source to the second power supply connection;

the collector of the first transistor being coupled to a laser diode connection to provide laser drive current thereto, and the collector of the second transistor being coupled to the first power supply connection;

the emitters of the third and fourth transistors being coupled to the second power supply connection;

the collectors of the third and fourth transistors being coupled to the bases of the first and second transistors, respectively;

the bases of the third an fourth transistors being coupled to receive a differential control voltage.

7. The improvement of claim 6 further comprised of an input circuit coupled to the bases of the first, second, third and fourth transistors to provide first and second control signals complimentary to third and fourth control signals, the first, second, third and fourth control signals being responsive to a differential input signal, the first and second control signals being coupled to the bases of the first and fourth transistors, respectively, and the third and fourth control signals being coupled to the bases of the second and third transistors, respectively.

8. The improvement of claim 6 wherein the emitters of the third and fourth transistors are coupled to the second power supply connection through a second current source.

9. The improvement of claim 6 further comprised of:

fifth and sixth transistors, each having an emitter, a base and a collector;

the collectors of the fifth and sixth transistors being coupled to the first power supply connection, the emitters of the fifth and sixth transistors being coupled to the collectors of the third and fourth transistors, respectively, and to the bases of first and second transistors, respectively; and

,

an input circuit coupled to the bases of the third, fourth, fifth and sixth transistors to provide first and second control signals complimentary to third and fourth control signals, the first, second, third and fourth control signals being responsive to a differential input signal, the first and second control signals being coupled to the bases of the fourth and fifth transistors, respectively, and the third and fourth control signals being coupled to the bases of the third and sixth transistors, respectively.

10. The improvement of claim 9 further comprised of second and third current sources coupled to the emitters of the fifth and sixth transistors, respectively.

11. The improvement of claim 9 further comprising a biasing circuit maintaining the voltage of the emitters of the first and second transistors relative to the voltage of the second power supply connection substantially independent of temperature variations.

12. The improvement of claim 11 wherein the emitters of the third and fourth transistors are coupled to the second power supply connection through a second current source.

13. The improvement of claim 6 further comprising

fifth, sixth, seventh and eighth transistors, each having an emitter, a base and a collector;

the emitters of the third and fourth transistors being coupled to the second power supply connection through a second current source;

the collectors of the fifth and sixth transistors being coupled to the first power supply connection, the emitters of the fifth and sixth transistors being coupled to the collectors of the third and fourth transistors, respectively, and to the bases of first and second transistors, respectively;

the emitters of the seventh and eighth transistors being coupled together and through a third current source to the second power supply terminal;

the collectors of the seventh and eighth transistors being coupled to the bases of the fifth and sixth transistors, respectively, and through first and second resistors to a common node, the common node being coupled to the first power supply connection through a third resistor

a fourth current source coupled between the common node and the second power supply connection; and

,

an input circuit coupled to the bases of the third, fourth, seventh and eighth transistors to provide first and second complimentary control signals, the first and second control signals being responsive to a differential input signal, the first control signal being coupled to the bases of the fourth and eighth transistors, respectively, and the second control signal being coupled to the bases of the third and seventh transistors, respectively.

14. The improvement of claim 13 wherein the second current source is a fourth resistor.

15. The improvement of claim 14 wherein the input circuit comprises a circuit for maintaining the average voltage of the bases of the third and fourth transistors substantially at the bandgap voltage of the transistors relative to the voltage of the second power supply connection.

16. The improvement of claim 15 further comprising a biasing circuit maintaining the voltage of the emitters of the first and second transistors relative to the voltage of the second power supply connection substantially independent of temperature variations.

17. The improvement of claim 13 further comprising:

ninth and tenth transistors, each having an emitter, a base and a collector;

fifth and sixth current sources;

the input circuit being coupled to the bases of the ninth and tenth transistors;

the ninth and tenth transistors having their collectors coupled to the first power supply connection and their emitters coupled to the bases of the fourth and the third transistors, respectively, and through the fifth and sixth current sources, respectively to the second power supply connection.

18. The improvement of claim 17 wherein the input circuit comprises:

eleventh, twelfth, thirteenth and fourteenth transistors, each having an emitter, a base and a collector;

fourth, fifth, sixth and seventh resistors; and

,

seventh, eighth, ninth, tenth, eleventh, twelfth and thirteenth current sources;

the eleventh and twelfth transistors having their emitters coupled together and through the seventh current source to the second power supply connection, their bases coupled to form differential inputs to the differential laser driver circuit, and their collectors coupled to the bases of the thirteenth and fourteenth transistors, respectively, to the second power supply connection through the eighth and ninth current sources, respectively, and through the fourth and fifth resistors respectively to the first power supply connection;

the thirteenth and fourteenth transistors having their collectors coupled to the first power supply connection, and their emitters coupled to the second power supply connection through the tenth and the eleventh current sources, and to the bases of the tenth and the ninth transistors, respectively, through the sixth and the seventh resistors, respectively;

the bases of the ninth and tenth transistors being coupled to the second power supply connection through the twelfth and thirteenth current sources, respectively.

19. The improvement of claim 18 wherein the second current source is a eighth resistor.

20. The improvement of claim 19 wherein the twelfth and thirteenth current sources have a temperature dependence maintaining the average voltage of the bases of the third and fourth transistors substantially at the bandgap voltage of the transistors relative to the voltage of the second power supply connection.

21. The improvement of claim 20 wherein the third and fourth current sources have a temperature dependence maintaining the voltage of the emitters of the first and second transistors relative to the voltage of the second power supply connection substantially independent of temperature variations.

22. The improvement of claim 19 wherein some of the current sources are variable to reduce the voltage swing on the bases of the first and second transistors and to reduce the common mode voltage on the bases of the third and fourth transistors.