Method and apparatus for a trace buffer in an emulation system

• US 5,884,066 A
• Filed: 05/14/1997
• Issued: 03/16/1999
• Est. Priority Date: 02/16/1994
• Status: Expired due to Term

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Quickturn Design Systems Incorporated (Cadence Group)
• Inventors: Kuijsten, Han
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): GARBOWSKI, LEIGH M
• Application Number:
  US08/855,908
• Time in Patent Office: 671 Days
• Field of Search: 395/500, 364/488, 364/489, 364/490, 364/491, 364/578
• US Class Current: 703/28
• CPC Class Codes: G06F 11/2268 Logging of test results
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A tracing method and apparatus for a digital emulation system. The invention allows trace information to be obtained during the emulation of a digital circuit that includes a clock signal. Input signal states are sensed and stored each clock cycle. The internal state of the emulated digital circuit is also stored. By using the stored input signal states and internal states, the states of other signals in the emulated digital circuit are derived.

Claims

1. A tracing system for tracing the operation of a digital circuit, the tracing system comprising:

a digital system for emulating the operation of the digital circuit, the digital system including a clock, inputs, internal signals and one or more state storage means for storing and indicating an electrical state;

implementation means coupled to the digital system for representing the logic of the digital circuit within the digital system;

input tracing means coupled to the digital system for sensing and storing the states of the inputs every clock cycle;

internal state tracing means coupled to the storage means in the digital system, for sensing and storing a state of a state storage means of the digital system every n clock cycles;

analysis means coupled to the digital system for deriving the state of one or more internal signals based on the stored internal states and the stored input states; and

output means coupled to the digital system for outputing the derived states of the internal signals.

2. The tracing system of claim 1, wherein the internal state tracing means senses and stores the internal state of the digital system by storing one or more internal signal states, wherein the signal states collectively determine the state of each of the storage elements in the digital circuit.

3. The tracing system of claim 1, wherein the digital system is two or more field programmable gate arrays.

4. The tracing system of claim 1, wherein the digital system is a general purpose computer executing software.

5. The tracing system of claim 1, wherein the digital system is a multiprocessor array.

6. The tracing system of claim 1, wherein the implementation means includes compiling the digital circuit design into a compiled design including one or more boolean logic definitions.

7. The tracing system of claim 6, wherein the analysis means uses the representation of the logic of the digital circuit within the digital system, the compiled design, the stored input states and the stored internal states to derive trace information.