Memory controller for controlling different memory types and generating uncorrectable error faults when an access operation is performed to a wrong type

• US 5,884,067 A
• Filed: 10/27/1995
• Issued: 03/16/1999
• Est. Priority Date: 12/22/1992
• Status: Expired due to Term

• Current Assignee: Bradley W. Hoffert, Mark A. Loomis, Shawn Fontaine Storm
• Original Assignee: Bradley W. Hoffert, Mark A. Loomis, Shawn Fontaine Storm
• Inventors: Hoffert, Bradley W., Loomis, Mark A., Storm, Shawn Fontaine
• Primary Examiner(s): Chan, Eddie P.
• Assistant Examiner(s): Nguyen, Hiep T.
• Application Number:
  US08/549,324
• Time in Patent Office: 1,236 Days
• Field of Search: 395/307, 395/433, 395/444, 395/405, 395/431, 395/432, 395/437, 395/445, 395/494, 395/250, 395/872, 395/800, 395/114, 395/115, 395/509, 395/510, 395/328, 395/526, 395/511 , 395/182.06, 395/185.01, 395/517, 365/222, 371/40.4, 371/49.2, 345/202
• US Class Current: 345/533
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory

Abstract

A memory controller method and apparatus wherein data to be written to a memory device is stored in a data queue, the data queue has a plurality of entries wherein at least two of the entries are combined to store a single datum, the single datum is wider than a single entry of the entries and addresses associated with the stored data of the data queue are stored in an address queue, thereby providing a circular write buffer. Specific memory modules of a plurality of memory modules to be refreshed are indicated to a refresh controller to thereby selectively control which of the memory modules are refreshed by the refresh controller. Access is controlled to the plurality of memory modules, each of the memory modules having an associated type. Configuration status information indicating the associated type for each of the memory modules is stored so that, if an access operation is performed to a wrong type, uncorrectable error faults are generated and can be detected. Planar data packing is performed by receiving a plurality of unpacked video data from the memory device, each of the unpacked video data having at least two channels of information, and packing the unpacked video data into packed video data by stripping at least one channel from each of the plurality of unpacked video data and then combining any remaining unstripped channel data, prior to sending the packed video data to a bus master. Planar data unpacking is performed by receiving the packed video data from the bus master, the packed video data having at least one missing channel of the at least two channels of the unpacked video data, and then expanding the packed video data to unpacked video data for storage in the memory device, thereby providing video data translation.

Claims

1. A memory controller, comprising:

a memory module access controller, controlling access to a plurality of memory modules, each of the memory modules having an associated type; and

a configuration status register, storing configuration status information indicating the associated type for each of the memory modules, the memory access controller controlling access to each memory module type, wherein if an access operation is performed to a wrong type, uncorrectable error faults are generated and can be detected, wherein if a video input/output access is performed to a dynamic random access memory (DRAM) type of memory module coupled to the memory controller through a bus, the memory module access controller will respond to the video input/output access to the DRAM type of memory module wherein the DRAM type of memory module is;

(1) prevented from being column address strobe (CAS) enabled to drive the bus, and (2) allowed to generate an row address strobe (RAS) pulse width that violates operating parameters for the DRAM type of memory module,

if a video random access memory (VRAM) access is performed to the dynamic random access memory (DRAM) type of memory module, the memory module access controller will respond to the VRAM access to the DRAM type of memory module wherein write enable is asserted to the DRAM type of memory module, and

if a dynamic random access memory (DRAM) store access is performed to a video type of memory module, the memory module access controller will respond to the DRAM store access to the video type of memory module wherein RAM output enable (ROE) is deasserted.

2. A memory controller method, comprising the steps of:

indicating to a refresh controller of any specific memory modules of a plurality of memory modules to be refreshed and thereby selectively controlling which of the memory modules are refreshed by the refresh controller;

controlling access to the plurality of memory modules, each of the memory modules having an associated type; and

storing configuration status information indicating the associated type for each of the memory modules wherein if an access operation is performed to a wrong type, uncorrectable error faults are generated and can be detected, wherein if a video input/output access is performed to a dynamic random access memory (DRAM) type of memory module, the video input/output access to the DRAM type of memory module will be controlled wherein (1) the DRAM type of memory module is not column address strobe (CAS) enabled to drive a bus coupling the memory controller to the DRAM type of memory module, and (2) an unblocked row address strobe (RAS) pulse width is generated that violates operating parameters for the DRAM type of memory module,

if a video random access memory (VRAM) access is performed to a dynamic random access memory (DRAM) type of memory module, the VRAM access to the DRAM type of memory module will be controlled wherein write enable is asserted to the DRAM type of memory module, and

if a dynamic random access memory (DRAM) store access is performed to a video type of memory module, the DRAM store access to the video type of memory module will be controlled wherein RAM output enable (ROE) is deasserted.

3. A memory controller, comprising:

a planar data packer to receive a plurality of unpacked video data from a memory device, each of the unpacked video data having at least two channels of information, and to pack the unpacked video data into packed video data by stripping at least one channel from each of the plurality of unpacked video data and then combining any remaining unstripped channel data, prior to sending the packed video data to a bus master;

a planar data unpacker to receive the packed video data from the bus master, the packed video data having at least one missing channel of the at least two channels of the unpacked video data, the planar data unpacker then unpacking the packed video data to unpacked video data for storage in the memory device; and

an error correction code (ECC) generator to generate ECC information to be appended to non-video data received from the bus master prior to sending the non-video data to the memory device, and to generate check ECC data to be compared with the ECC information appended to the non-video data received from the memory device prior to sending the non-video data to the bus master.

4. The memory controller as set forth in claim 3 wherein the ECC information to be appended to the non-video data can be inspected prior to sending the non-video data to the memory device and can be inspected after the non-video data has been received from the memory device.

5. The memory controller as set forth in claim 3 wherein override ECC information can be appended to the non-video data, in place of the ECC information generated by the ECC generator, prior to writing the non-video data to the memory device.

6. The memory controller as set forth in claim 3 wherein comparison of the check ECC data to the ECC information appended to the non-video data can be turned off.

7. A memory controller method, comprising the steps of:

planar data packing by receiving a plurality of unpacked video data from a memory device, each of the unpacked video data having at least two channels of information, and packing the unpacked video data into packed video data by stripping at least one channel from each of the plurality of unpacked video data and then combining any remaining unstripped channel data, prior to sending the packed video data to a bus master;

planar data unpacking by receiving the packed video data from the bus master, the packed video data having at least one missing channel of the at least two channels of the unpacked video data, and then unpacking the packed video data to unpacked video data for storage in the memory device, thereby providing video data translation;

generating error correction code (ECC) information to be appended to non-video data received from the bus master prior to sending the non-video data to the memory device; and

generating check ECC data to be compared with the ECC information appended to the non-video data received from the memory device prior to sending the non-video data to the bus master.

8. The memory controller method as set forth in claim 7, further comprising the steps of:

inspecting the ECC information to be appended to the non-video data prior to sending the non-video data to the memory device;

inspecting the ECC information appended to the non-video after the non-video data has been received from the memory device.

9. The memory controller method as set forth in claim 7, further comprising the step of:

appending override ECC information to the non-video data, in place of the ECC information generated by the ECC generator, prior to writing the non-video data to the memory device.

10. The memory controller method as set forth in claim 7 wherein comparison of the check ECC data to the ECC information appended to the non-video data can be turned off.

11. A memory controller comprising:

a circular write buffer including a data queue storing all data to be written to a memory device, the data queue having a plurality of entries wherein at least two of the entries are combined to store a single datum, the single datum being larger than a single entry of the entries, and an address queue storing addresses associated with the stored data of the data queue;

a refresh controller to control refresh of a plurality of memory modules;

a control status register to indicate to the refresh controller of any specific memory modules of the plurality of memory modules to be refreshed and selectively control which of the memory modules are refreshed by the refresh controller;

a memory module access controller, controlling access to the plurality of memory modules, each of the memory modules having an associated type;

a configuration status register, storing configuration status information indicating the associated type for each of the memory modules, the memory access controller controlling access to each memory module type, wherein if an access operation is performed to a wrong type, uncorrectable error faults are generated and can be detected; and

a video data translator having a planar data packer to receive a plurality of unpacked video data from the memory device, each of the unpacked video data having at least two channels of information, and to pack the unpacked video data into packed video data by stripping at least one channel from each of the plurality of unpacked video data and then combining any remaining unstripped channel data, prior to sending the packed video data to a bus master, the video data translator also having a planar data unpacker to receive the packed video data from the bus master, the packed video data having at least one missing channel of the at least two channels of the unpacked video data, the planar data unpacker then unpacking the packed video data to unpacked video data for storage in the memory device.

12. A memory controller method comprising the steps of:

storing all data to be written to a memory device in a data queue, the data queue having a plurality of entries wherein at least two of the entries are combined to store a single datum, the single datum being larger than a single entry of the entries and storing addresses associated with the stored data of the data queue in an address queue, thereby providing a circular write buffer;

storing information indicating to a refresh controller of any specific memory modules of a plurality of memory modules to be refreshed to selectively control which of the memory modules are refreshed by the refresh controller;

controlling access to the plurality of memory modules, each of the memory modules having an associated type; and

storing configuration status information indicating the associated type for each of the memory modules wherein if an access operation is performed to a wrong type, uncorrectable error faults are generated and can be detected;

planar data packing by receiving a plurality of unpacked video data from the memory device, each of the unpacked video data having at least two channels of information, and packing the unpacked video data into packed video data by stripping at least one channel from each of the plurality of unpacked video data and then combining any remaining unstripped channel data, prior to sending the packed video data to a bus master; and

planar data unpacking by receiving the packed video data from the bus master, the packed video data having at least one missing channel of the at least two channels of the unpacked video data, and then unpacking the packed video data to unpacked video data for storage in the memory device, thereby providing video data translation.