Lateral trench MISFET and method of manufacturing the same

• US 5,885,878 A
• Filed: 03/31/1997
• Issued: 03/23/1999
• Est. Priority Date: 10/25/1994
• Status: Expired due to Term

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Fujishima, Naoto, Kitamura, Akio
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Murphy, John
• Application Number:
  US08/829,751
• Time in Patent Office: 722 Days
• Field of Search: 438/302, 438/303, 438/304, 438/306, 438/307, 438/176, 438/192, 438/221, 438/225, 438/229, 438/230, 438/236, 438/296, 438/297, 438/298, 257/335, 257/336, 257/341, 257/342, 257/343, 257/344
• US Class Current: 438/302
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7801 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region lateral high-voltage MISFETs with channel well and drain offset region H01L29/7835
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: Y10S 148/126 Power FETs
• CPC Class Codes: Y10S 148/151 Simultaneous diffusion

Abstract

To provide a lateral MISFET that has a uniform and reliable gate insulation film, and exhibits low on-resistance and excellent balance between the breakdown voltage and on-resistance. The device of the invention has an n-type semiconductor substrate, in a part of the surface layer thereof is formed a trench. An n-drain region is formed in the bottom of the trench. A side wall oxide film is formed on the side face of the trench. The trench is filled with a conductive material, on which is formed a drain electrode. A p-base region and an n-source region are self-aligned on the portion of the substrate in which the trench is not formed. A MIS gate is disposed on the p-base region. Since the portion of the substrate along the side wall oxide film functions as a drain drift region, the unit cell dimension are greatly reduced, the on-resistance is reduced, and therefore the trade-off relation between the breakdown voltage and the on-resistance is improved.

Claims

1. A method of manufacturing a lateral trench MISFET, comprising the steps of:

providing a semiconductor layer of a first conductivity type;

forming a trench in a surface layer of the semiconductor layer by etching utilizing a mask;

forming a drain region of the first conductivity type in a bottom of said trench by ion implantation and subsequent diffusion;

burying a conductive material in said trench;

flattening surfaces of said semiconductor layer and said conductive material, thereby exposing a surface of a portion of said semiconductor layer separate from the trench;

forming a gate insulation film on the surface of the portion of the semiconductor layer separate from the trench;

forming a gate electrode on said gate insulation film;

forming a base region of the second conductivity type and a source region of the first conductivity type in said semiconductor layer, by utilizing said gate electrode as a mask for self-alignment;

forming an inter-layer insulation film on said gate electrode;

opening contact holes in said inter-layer insulation film; and

disposing drain and source electrodes in said contact holes.

2. The method of claim 1, further comprising the step of forming a side wall region of the second conductivity type in a side face of said trench by oblique ion implantation at an oblique angle to said side face, and by subsequent diffusion.