Integrated arc and polysilicon etching process

• US 5,885,902 A
• Filed: 11/05/1997
• Issued: 03/23/1999
• Est. Priority Date: 11/08/1995
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Blasingame, Tom, Gupta, Subash, Bell, Scott A.
• Primary Examiner(s): Nguyen, Nam
• Assistant Examiner(s): VERSTEEG, STEVEN H
• Application Number:
  US08/964,855
• Time in Patent Office: 503 Days
• Field of Search: 438/719, 438/725, 438/738, 438/742, 438/952
• US Class Current: 438/738
• CPC Class Codes: H01L 21/0276 using an anti-reflective coating anti-reflective coating for lithography in general G03F7/09
• CPC Class Codes: H01L 21/31138 by dry-etching
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: Y10S 438/95 Multilayer mask including nonradiation sensitive layer
• CPC Class Codes: Y10S 438/952 Utilizing antireflective layer

Abstract

A composite of an anti-reflective coating on polysilicon is accurately etched to form a polysilicon pattern by initially etching the ARC with gaseous plasma containing helium and/or nitrogen which is substantially inert with respect to polysilicon.

Claims

1. A method of manufacturing a semiconductor device, which method comprises:

depositing a layer of polysilicon on a dielectric layer;

depositing a dielectric anti-reflective coating on the polysilicon layer;

etching the dielectric anti-reflective coating with a first etchant comprising an inert gaseous plasma containing either helium, nitrogen, or a mixture thereof, which does not substantially etch the polysilicon layer; and

etching the polysilicon layer with a second etchant to form a pattern.

2. The method according to claim 1, wherein the polysilicon layer has a non-planar surface topography and the dielectric anti-reflective coating has a resulting non-uniform thickness due to the non-planar surface topography of the polysilicon layer.

3. The method according to claim 2, comprising etching the polysilicon layer with a second etchant to form a conductive pattern comprising a plurality of gate electrodes having substantially similar etch profiles.

4. The method according to claim 1, wherein the dielectric anti-reflective coating and the polysilicon layer are etched in the same chamber.

5. The method according to claim 4, wherein the dielectric anti-reflective coating and polysilicon layers are sequentially etched without conducting an intervening step to remove polymeric material from the polysilicon layer and/or the chamber.

6. The method according to claim 1, wherein the first etchant comprises a gaseous plasma containing nitrogen with or without an inert gas.

7. The method according to claim 1, wherein the dielectric anti-reflective coating comprises an organic or organometallic material.

8. The method according to claim 1, comprising etching the polysilicon layer with a second etchant to form a pattern comprising a gate electrode.

9. The method according to claim 8, wherein the gate electrode has a substantially uniform etch profile.

10. The method according to claim 1, comprising etching the polysilicon layer with a second etchant to form a conductive pattern comprising a plurality of gate electrodes having substantially similar etch profiles.