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Self-reconfigurable parallel processor made from regularly-connected self-dual code/data processing cells

  • US 5,886,537 A
  • Filed: 05/05/1997
  • Issued: 03/23/1999
  • Est. Priority Date: 05/05/1997
  • Status: Expired due to Term
First Claim
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1. A programmable logic device comprising:

  • (a) a first plurality of input channels,(b) a means of computing the value of a binary state variable from said first plurality of input channels,(c) an internal storage memory accessible as either a serial read serial write shift register or as a parallel read random access memory, depending on the value of said binary state variable,(d) a second plurality of input channels which correspond one to one with said first plurality of input channels,(e) a means of combining said first plurality of input channels and said second plurality of input channels to specify serial input data for said shift register,(f) a means of addressing said random access memory using said second plurality of input channels,(g) a plurality of output channels, each of which correspond to either one of said first plurality of input channels or one of said second plurality of input channels,(h) a means of setting the values of said plurality of output channels by combining said first plurality of input channels with either the serial output or parallel outputs of said internal storage memory, depending on the value of said binary state variable, and(i) a means of shifting said shift register'"'"'s contents based on the value of said binary state variable and an externally applied dock,whereby said programmable logic device can map inputs to output via said internal storage memory, or can present the contents of said memory to certain of its outputs and can load the contents of said memory from certain of its inputs.

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