Combined logic gate and latch

• US 5,886,541 A
• Filed: 08/05/1996
• Issued: 03/23/1999
• Est. Priority Date: 08/05/1996
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Asato, Creigton
• Primary Examiner(s): SANTAMAURO, JON P
• Application Number:
  US08/692,541
• Time in Patent Office: 960 Days
• Field of Search: 326/95-98, 326/112, 326/119, 326/121, 326/17, 326/27, 326/93, 327/219, 327/436
• US Class Current: 326/93
• CPC Class Codes: H03K 3/037 Bistable circuits
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit

Abstract

A circuit combines the functions of a logic gate and a latch to lower steady state power dissipation during gate operation. The circuit operates in two modes: a flow-through mode and a latched mode. In the flow-through mode, a gate portion which receives one or more digital input signals implements the complement of a desired Boolean logic function on the input signals and provides an internal signal. The gate portion may have a steady-state power dissipation while providing the internal signal. An inverter in a latch portion of the circuit inverts the internal signal to generate an output signal which represents the desired logical combination of the input signals. The inverter provides the output signal with a full-range CMOS voltage. In latched mode, the gate portion is disabled to stop the steady-state power dissipation while the latch portion of the circuit preserves the desired output signal.

Claims

1. A circuit comprising:

a latch;

a logic gate having an output terminal coupled to an input terminal of the latch, wherein when input signals to the logic gate are selected constant voltages, the logic gate dissipates power while power through the logic gate is enabled;

a first switching circuit coupled to disable power through the logic gate when the latch operates in a latched mode and enable power through the logic gate when the latch operates in a flow-through mode; and

a second switching circuit coupled between the logic gate and the input terminal of the latch, wherein the second switching circuit connects the logic gate to the latch when the latch operates in the flow-through mode and disconnects the logic gate from the latch when the latch operates in the latched mode.

2. The circuit of claim 1, wherein:

the first switching circuit comprises a first transistor coupled between the input terminal of the latch and a source of a first voltage, wherein the first transistor is closed when the latch operates in the flow-through mode and open when the latch operates in the latched mode; and

the logic gate comprises a network of transistors coupled between the input terminal of the latch and a source of a second voltage.

3. The circuit of claim 2, wherein the first voltage is a supply voltage for the circuit and the second voltage is a ground voltage for the circuit.

4. The circuit of claim 2, wherein the input signals are applied to gates of transistors in the network, and the network conducts when a Boolean operation on states of the input signals has a first result and the network does not conduct when the Boolean operation on the states of the input signals has a second result that differs from the first result.

5. The circuit of claim 4, wherein the second switching circuit comprises a second transistor coupled between the network and the input terminal of the latch, wherein the second transistor is closed when the latch operates in the flow-through mode and open when the latch operates in the latched mode.

6. The circuit of claim 2, wherein:

the latch comprises a first inverting circuit and a second inverting circuit;

the input terminal of the latch is coupled to an input terminal of the first inverting circuit;

an output terminal of the first inverting circuit is coupled to an input terminal of the second inverting circuit; and

the switching circuit further comprises means for applying an output voltage from the second inverting circuit to the input terminal of the first inverting circuit when operating the latch in latched mode.

7. The circuit of claim 6, wherein the first inverting circuit is an inverter.

8. The circuit of claim 7, wherein the second inverting circuit is an inverter.

9. The circuit of claim 6, wherein the second inverting circuit is tri-state buffer.

10. The circuit of claim 1, wherein:

the first and second switching circuits are connected in series between a source of a first voltage and a first node;

the latch is connected to a second node that is between the first and second switching circuits; and

the logic gate comprises a network of transistors coupled between the first node and a source of a second voltage.

11. The circuit of claim 1, wherein:

the first and second switching circuits are connected in series between a source of a first voltage and the input terminal of the latch;

the logic gate comprises a network of transistors coupled between a second node and a source of a second voltage, the second node being between the first switching circuit and the second switching circuit.

12. The circuit of claim 1, wherein the logic gate performs a logical AND operation on a first input signal and a second input signal to the logic gate.