Enabling clock signals with a phase locked loop (PLL) lock detect circuit

• US 5,886,582 A
• Filed: 08/07/1996
• Issued: 03/23/1999
• Est. Priority Date: 08/07/1996
• Status: Expired due to Term

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Stansell, Galen E.
• Primary Examiner(s): MIS, DAVID C
• Application Number:
  US08/693,735
• Time in Patent Office: 958 Days
• Field of Search: 331/1 A, 331/2, 331/11, 331/12, 331/14, 331/17, 331/18, 331/25, 331/DIG. 2, 327/142, 327/143, 327/156-159, 327/218, 327/299, 327/147-150
• US Class Current: 331/1.00A
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/089 the phase or frequency detector generating up-down pulses H03L7/087 takes precedence
• CPC Class Codes: H03L 7/095 using a lock detector H03L7/087 takes precedence
• CPC Class Codes: Y10S 331/02 Phase locked loop having lock indicating or detecting means

Abstract

A circuit for enabling and disabling generation of an output clock signal is disclosed. The circuit includes a PLL lock detect circuit that generates an active lock control signal when an output reference signal of a phase lock loop (PLL) circuit is phase locked relative to an input reference signal to the PLL. The output reference signal of the PLL, and the lock signal from the lock detect circuit, are both provided to a clock enable circuit. The clock enable circuit includes a negative edge-triggered D-type flip-flop and a two-input AND gate. The lock signal is applied to the D-input of the flip-flop, while the clock signal is applied to the clock input of the flip-flop. The lock signal is generated asynchronously relative to the input clock signal. Therefore, the flip-flop samples the lock signal on each falling edge of the clock signal so as to synchronize the lock signal relative to the input clock signal. The sampled lock signal, and the input clock signal (formed from the PLL output reference signal) are provided on respective input terminals of the AND gate. The output of the AND gate defines the output clock signal.

Claims

1. A method of operating a clock signal generator comprising the step of:

generating a lock signal in response to (i) a window signal and (ii) one or more control signals; and

generating an output clock signal in response to (i) an input clock signal and (ii) said lock signal, wherein said lock signal corresponds to a lock state of a phase locked loop (PLL).

2. The method of claim 1 wherein said step of generating the output clock signal includes the substep of:

blanking the output clock signal when the lock signal is in an inactive state indicative of a condition where the PLL is unlocked.

3. The method of claim 1 wherein said step of generating the output clock signal includes the substep of:

generating the output clock signal in a valid state when the lock signal is in an active state indicative of a condition where the PLL is locked.

4. The method of claim 1 wherein said step of generating the output clock signal includes the substep of:

disjunctively combining the input clock signal and the lock signal so that when the lock signal is in an inactive state the output clock signal is blanked and when the lock signal is in an active state the output clock signal is generated in a valid state.

5. The method of claim 1 further comprising the step of:

synchronizing the lock signal with respect to the input clock signal to generate a synchronized lock signal to thereby prevent generation of an initial foreshortened pulse portion of the output clock signal; and

wherein said step of generating the output clock signal includes the substep of disjunctively combining the input clock signal and the synchronized lock signal so that when the synchronized lock signal is in an inactive state the output clock signal is blanked and when the synchronized lock signal is in an active state the output clock signal is generated in a valid state.

6. The method of claim 1 further comprising the steps of:

applying an input reference signal to the PLL; and

,

generating the lock signal when an output reference signal of the PLL is phase locked relative to the input reference signal.

7. The method of claim 6 wherein the output reference signal defines the input clock signal.

8. The method of claim 6 further including the steps of:

varying the input reference signal to the PLL to thereby effect frequency slewing in the output reference signal;

generating the lock signal in an inactive state when the output reference signal of the PLL is out-of-lock relative to the input reference signal; and

,

wherein said step of generating the output clock signal includes the substep of blanking the output clock signal when the lock signal is in the inactive state.

9. The method of claim 1 further comprising the steps of:

applying an input reference signal to the PLL;

generating the lock signal when an output reference signal of the PLL is outside of a predetermined tolerance defined by said window signal;

synchronizing the lock signal with respect to the input clock signal to generate a synchronized lock signal, said output reference signal defining the input clock signal; and

,

wherein said step of generating said output clock signal includes the substep of disjunctively combining the input clock signal and the synchronized lock signal so that when the synchronized lock signal is in an inactive state the output clock signal is blanked and when the synchronized lock signal is in an active state the output clock signal is generated in a valid state.

10. The method of claim 1 wherein the PLL is a primary PLL, said method further including the steps of:

applying an input reference signal to the primary PLL and a secondary PLL;

generating a power-on-reset signal when a secondary PLL output reference signal is phase locked to the input reference signal;

generating the lock signal in an active state when the primary PLL output reference signal is phase locked to the input reference signal and the power-on-reset signal is in an active state; and

,

maintaining the lock signal in the active state while frequency slewing.

11. A clock circuit comprising:

means for generating a lock signal in response to (i) a window signal and (ii) one or more control signals, said lock signal corresponding to a lock state of a phase locked loop (PLL) when an output reference signal of said PLL is phase locked relative to an input reference signal of said PLL; and

,

means responsive to an input clock signal for generating an output clock signal according to a control signal corresponding to said lock signal.

12. The clock circuit of claim 11 further including:

means for synchronizing said lock signal with respect to the input clock signal to generate a synchronized lock signal wherein said synchronized lock signal defines said control signal.

13. The clock circuit of claim 12 wherein said lock signal generating means includes a lock detector for generating the lock signal according to a lock indicative signal produced by said PLL representative of the extent to which said output reference signal is phase locked relative to said input reference signal.

14. The clock circuit of claim 12 wherein said output clock signal generating means includes an AND gate having a pair of input terminals for receiving said control signal and said input clock signal.

15. The clock circuit of claim 12 wherein said sychronizing means includes a D-type flip flop having a data input terminal for receiving said lock signal, a clock terminal for receiving said input clock signal, and a data output terminal for outputting said sychronized lock signal defining said control signal.

16. The clock circuit of claim 12 wherein said PLL is a primary PLL, said output reference signal is a primary PLL output reference signal, said primary PLL including an output terminal for generating a primary lock indicative signal, and said lock signal generating means comprises a primary lock detector responsive to said primary lock indicative signal, said clock circuit further including:

a secondary PLL responsive to said input reference signal for generating a secondary PLL output reference signal and a secondary lock indicative signal on respective output terminals thereof; and

,

a secondary lock detector responsive to said secondary lock indicative signal for generating a power-on-reset signal indicative of a lock state of said secondary PLL;

wherein said primary lock detector is configurable to generate said lock signal in an active state when said primary PLL output reference signal is phase locked to said input reference signal and said power-on-reset signal is in an active state; and

, wherein said primary PLL includes means for maintaining said lock signal in said active state while frequency slewing.

17. A clock circuit comprising:

a lock detector having an output terminal for generating a lock signal in response to (i) a window signal and (ii) one or more control signals, said lock signal corresponding to a lock state of a phase locked loop (PLL) when an output reference signal of said PLL is phase locked relative to an input reference signal of said PLL; and

,

a logic gate having a first input terminal for receiving an input clock signal and a second input terminal for receiving a control signal corresponding to said lock signal, said logic gate having an output terminal for generating an output clock signal in a valid state when said control signal is in an active state indicative of a lock state where said PLL is locked, said logic gate blanking said output clock signal when said control signal is in an inactive state indicative of a lock state where said PLL is unlocked.

18. The clock circuit of claim 17 further including:

a synchronizing circuit configured to synchronize said lock signal relative to said input clock signal to generate a synchronized lock signal wherein said synchronized lock signal defines said control signal.

19. The clock circuit of claim 18 wherein said lock detector generates said lock signal according to a lock indicative signal produced by said PLL representative of the extent to which said output reference signal is phase locked relative to said input reference signal.

20. The clock circuit of claim 18 wherein said logic gate comprises an AND gate having a pair of input terminals for receiving said control signal and said input clock signal.

21. The clock circuit of claim 18 wherein said synchronizing circuit includes a D-type flip flop having a data input terminal for receiving said lock signal, an clock terminal for receiving said input clock signal, and a data output terminal for outputting said synchronized lock signal defining said control signal.

22. The clock circuit of claim 18 wherein said lock detector generates said lock signal according to a lock indicative signal produced by said PLL representative of the extent to which said output reference signal is phase locked relative to said input reference signal, said logic gate comprises an AND gate having a pair of input terminals for receiving said control signal and said input clock signal, and said synchronizing circuit includes a D-type flip flop having a data input terminal for receiving said lock signal, an clock terminal for receiving said input clock signal, and a data output terminal for outputting said synchronized lock signal defining said control signal.