Graphics rendering device and method for operating same

• US 5,886,701 A
• Filed: 06/27/1996
• Issued: 03/23/1999
• Est. Priority Date: 08/04/1995
• Status: Expired due to Term

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Scott, George Easton III, Good, Howard, Chauvin, Joseph W., Toelle, Michael A., Griffin, Kent E., Kenworthy, Mark L., Powell, William Chambers III, Veres, James E., Gabriel, Steven A., Torborg, John G. Jr.
• Primary Examiner(s): Nguyen, Phu K.
• Application Number:
  US08/672,086
• Time in Patent Office: 999 Days
• Field of Search: 345/418-20, 345/426-38, 345/501-7
• US Class Current: 345/418
• CPC Class Codes: G06T 11/40 Filling a planar surface by adding surface attributes, e.g. colour or texture
• CPC Class Codes: G06T 13/80 2D [Two Dimensional] animation, e.g. using sprites
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 15/04 Texture mapping
• CPC Class Codes: G06T 15/60 Shadow generation

Abstract

A graphics rendering chip serially renders a stream of geometric primitives to image regions called chunks. A set-up processor in the chip parses rendering commands and the stream of geometric primitives and computes edge equation parameters. A scan-convert processor receives the edge equation parameters from the set-up processor and scan converts the geometric primitives to produce pixel records and fragment records. An internal, double-buffered pixel buffer stores pixel records for fully covered pixel addresses and also stores references to fragment lists stored in a fragment buffer. A pixel engine performs hidden surface removal and controls storage of pixel and fragment records to the pixel and fragment buffers, respectively. An anti-aliasing engine resolves pixel data for one pixel buffer while the pixel engine fills the other pixel buffer with pixel data for the next chunk.

Claims

1. A tiler for receiving geometric primitives representing three dimensional objects and rendering commands and for generating rendered image data to a two-dimensional image comprising a two dimensional array of pixel locations subdivided into contiguous sub-regions, the tiler comprising:

a memory interface controller for reading the geometric primitives and the rendering commands;

a set-up processor in communication with the memory interface controller for receiving a subset of the geometric primitives for each of the sub-regions of the image, parsing the rendering commands, and computing edge equation parameters;

a scan-convert processor in communication with the set-up processor for receiving the equation parameters for the geometric primitives, and for scan converting the geometric primitives to produce pixel data including color, depth, and coverage data for pixel locations in each sub-region of the image, where the scan-convert processor is capable of generating two or more fragments including color, depth, and coverage data for each pixel location in the the sub-regions;

a rasterization buffer for storing pixel data only for the pixel locations in the a sub-region currently being rasterized;

a pixel engine for receiving the pixel data, for controlling the transfer of the pixel data to the rasterization buffer such that potentially visible fragments are stored for each of a plurality of pixel locations of the sub-region in the rasterization buffer; and

an anti-aliasing engine for resolving pixel data stored in the rasterization buffer, including the potentially visible fragments, such that the potentially visible fragments are combined into a single set of color values per pixel location in the sub-region and the anti-aliased sub-region is transferred to a memory device,

wherein the sub-regions of the image are rendered serially and fragments are stored for only one sub-region at a time in the rasterization buffer.

2. The tiler of claim 1 wherein the set-up processor includes a vertex input processor for parsing the rendering commands.

3. The tiler of claim 1 wherein the set-up processor includes vertex registers for storing vertex data for a geometric primitive.

4. The tiler of claim 1 further including a texture read queue for storing read requests for texture data and a texture address generator in communication with the texture read queue, wherein the set-up processor is in communication with the texture read queue for issuing the texture read requests, and the texture address generator is in communication with the texture read queue for determining memory addresses of blocks of the texture data, which are distributed in a memory device in non-contiguous blocks of memory.

5. The tiler of claim 1 wherein the scan-convert processor includes primitive registers for storing the equation parameters.

6. The tiler of claim 1 further including:

a texture cache in communication with the memory control interface for storing texture data,

and a texture filter in communication with the texture cache for processing texture data to compute texture color data for pixel locations;

wherein the set-up processor is communication with the memory control interface for issuing requests for the texture data, the scan-convert processor is in communication with a texture filter for receiving the texture color data and producing the pixel data from the texture color data, and the set-up processor is capable of retrieving previously rendered sub-regions of the image as the texture data.

7. The tiler of claim 6 further including:

a decompression engine in communication with the memory control interface for decompressing independently accessible blocks of compressed texture data.

8. The tiler of claim 1 wherein the rasterization buffer includes a pixel buffer for storing color depth data for pixel locations in the chunk, and a fragment buffer for storing color, coverage, and depth data for partially covered pixel locations corresponding to the pixel locations in the chunk.

9. The tiler of claim 8 wherein the fragment buffer stores fragment records for a pixel location in a linked list.

10. The tiler of claim 1 firther including a compression engine in communication with the anti-aliasing engine for compressing the resolved pixel data, wherein the compression engine is capable of compressing each of the sub-regions such that the anti-aliased pixel data for each of the compressed sub-regions is independently accessible in the memory device.

11. The tiler of claim 1 wherein the tiler stores the rendered pixel data for each of the sub-regions in non-contiguous memory blocks distributed among memory locations in the memory device and updates a data structure for the image indicating where the pixel data for each sub-region is stored.

12. A tiler for rendering sets of geometric primitives to image chunks, the tiler comprising:

a set-up engine for receiving geometric primitives and rendering commands for a chunk, parsing the rendering commands, and queuing the geometric primitives in primitive registers;

a scan convert engine in communication with the set-up engine for receiving the geometric primitives, and for scan converting the geometric primitives to produce pixel data including color, depth, texture coordinates, and coverage data for pixel locations in the chunk;

a FIFO pixel queue in communication with the rasterizer for storing the color, depth, texture coordinates and coverage data for the pixel locations in the chunk;

a texture cache;

a texture cache control in communication with the scan convert engine for receiving the texture coordinates from the scan convert engine and in communication with a texture memory and the texture cache for fetching texture blocks from the texture memory and storing the texture blocks in the texture cache;

a texture filter engine in communication with the FIFO pixel queue and the texture cache for receiving color data and texture coordinates from the FIFO pixel queue, for filtering the texture samples in a corresponding texture block stored in the texture cache to compute filtered pixel values for the pixel locations in the chunk, and for modulating the color data with the filtered pixel values to compute composed pixel values;

a pixel buffer;

a fragment buffer;

a pixel engine in communication with the texture filter engine, and the FIFO pixel queue, for receiving generated pixels including the composed pixel values, coverage data, and depth data for pixel locations in the chunk, and in communication with the pixel and fragment buffers for performing depth compare operations between the depth data of the generated pixels with depth data of previously generated pixels stored in the pixel and fragment buffers, and for controlling storage of the generated pixels in the pixel and fragment buffers; and

an anti-aliasing engine in communication with the fragment and pixel buffers for receiving the stored pixel data in the pixel and fragment buffers and for resolving the pixel data to compute final pixel values for pixel locations in the chunk after the scan convert engine and the texture filter engine have converted the geometric primitives for the chunk into the pixel data.

13. The tiler of claim 12 wherein the pixel buffer includes two buffers, each sized to store color, depth, and alpha data and a pointer to a fragment list in the fragment buffer for each pixel location in the chunk;

and wherein the anti-aliasing engine is operable to resolve pixel data stored in one of the two buffers and corresponding fragment lists while the pixel engine stores generated pixel data for a subsequent chunk in the other pixel buffer and the fragment buffer.

14. The tiler of claim 12 further including a decompression engine in communication with the texture memory for receiving compressed texture blocks from texture memory, for decompressing the compressed texture blocks, and for transferring the decompressed texture blocks to the texture cache under control of the texture cache control.

15. The tiler of claim 14 wherein the texture memory stores a gsprite in compressed form, the gsprite comprises chunks and associated chunk control blocks, the chunk control blocks comprise pointers to the compressed texture blocks, and the texture cache control is communication with the texture memory for reading the chunk control blocks and fetching the compressed texture blocks using the pointers to locate the compressed texture blocks in the texture memory.

16. The tiler of claim 15 wherein the decompression engine includes a Huffinan/RLE decoder for decoding compressed texture data, and an inverse quantizer for multiplying frequency components of each texture block by quantization factors.

17. The tiler of claim 15 wherein the chunk control blocks each store indices to quantization factors used to decompress compressed texture blocks in corresponding chunks in the gsprite.

18. The tiler of claim 12 further including a compression engine in communication with the anti-aliasing engine for receiving the final pixel values and for compressing blocks of the final pixel values.

19. The tiler of claim 18 wherein the decompression engine is operable to perform both lossless and lossy forms of compression.

20. The tiler of claim 19 wherein the lossy form of compression includes a discrete cosine transform to generate coefficients and a quantization of the coefficients for each block.

21. The tiler of claim 19 wherein the lossless form of compression includes Huffinan and run length encoding.

22. A method for rendering objects for a scene to generate a display image at a frame rate, the method comprising:

assigning geometric primitives of the objects among the two or more chunks representing 2D arrays of image samples;

serially rendering the two or more chunks for at least two objects in the scene to produce a rendered image, the serial rendering step including the step of scan converting geometric primitives associated with a first chunk to produce per-sample subpixel data for image samples in the first chunk, and then resolving pixel data including the per-sample subpixel data from the first chunk, and repeating the scan converting and resolving steps for subsequent chunks of the two or more chunks such that per-sample subpixel data is used to perform antialiasing and is maintained for only one chunk at a time;

storing the resolved pixel data for the at least two objects; and

transferring the rendered image to the physical output device at the frame rate.

23. A method for compressing image data in a real-time graphics rendering pipeline in which geometric primitives in a view volume are rendered to generate a display image for a view space at a computational rate, the method comprising:

assigning the geometric primitives in the view volume to two or more corresponding chunks in the view space;

serially rendering the geometric primitives to the two or more corresponding chunks in a computational period including;

rasterizing a first set of geometric primitives corresponding to a first chunk to generate pixel data including pixel fragments having color, coverage, and depth data for pixel locations in the first chunk, resolving the pixel data for the first chunk to compute a color value for the pixel location in the first chunk, and storing resolved pixel data for the first chunk, and repeating the rasterizing, resolving and storing steps for one or more subsequent chunks such that pixel fragments used to perform antialiasing are maintained for only one chunk at a time; and

combining the resolved pixel data to generate a display image.

24. A graphics rendering system for serially rendering object geometry in a scene to a view space, the system comprising:

a memory for storing rendered image data;

an image pre-processor operable to transform the object geometry to the view space, and operable for sorting the transformed object geometry among plural chunks of the view space corresponding to 2D arrays of image samples;

an image processor communicative with the image pre-processor for receiving the transformed object geometry for the plural chunks, operable to serially render the transformed object geometry for the plural chunks to compute pixel values and per sample subpixel data for pixel locations in one chunk at a time, and operable to perform antialiasing by resolving the per sample subpixel data for the chunk such that per sample subpixel data is maintained for only one chunk at a time, and communicative with the memory to store the pixel values for the plural chunks in the memory.