Voltage multiplier with low threshold voltage sensitivity

• US 5,886,887 A
• Filed: 03/26/1998
• Issued: 03/23/1999
• Est. Priority Date: 03/27/1997
• Status: Expired due to Term

• Current Assignee: Integrated Memory Technologies Incorporated
• Original Assignee: Integrated Memory Technologies Incorporated
• Inventors: Jenq, Ching-Shi
• Primary Examiner(s): BERHANE, ADOLF D
• Application Number:
  US09/049,283
• Time in Patent Office: 362 Days
• Field of Search: 363/59, 363/60, 307/109, 307/110, 327/530, 327/536, 327/537
• US Class Current: 363/60
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type

Abstract

A voltage multiplier has a number of electrically-like stages. Each of the stages receives two input signals and a pump signal. The stage has an MOS transistor with a first source/drain region and a second source/drain region and a gate. Each stage also has means for receiving a pump signal and for separately pumping the first source/drain region and the gate of the first transistor by the pump signal. The two input signals are supplied to the first source/drain region and the gate of the first transistor, respectively. A first output signal is supplied from the second source/drain region of the first transistor, and from the first source/drain region of the first transistor. A voltage signal is supplied as the input signal of the first stage and a clock signal having a first phase is supplied to the first stage as the pump signal of the first stage. The first and second output signals of the first stage are supplied to the second stage as the input signals of the second stage and a clock signal having a second phase different from the first phase is supplied to the second stage as the pump signal of the second stage.

Claims

1. A voltage multiplier comprising:

a plurality of electrically connected like stages including at least a first stage and a second stage;

each of said first and second stages for receiving a first input signal, a second input signal, and a pump signal, and comprises;

a first transistor having a first terminal, a third terminal, a channel therebetween, and a second terminal for controlling the flow of current between the first terminal and the third terminal;

means for receiving said pump signal and for separately pumping said first terminal and said second terminal of said first transistor by said pump signal;

said first input signal supplied to said first terminal and said second input signal supplied to said second terminal of said first transistor;

a first output signal supplied from said third terminal of said first transistor;

a second output signal supplied from said first terminal of said first transistor;

wherein a voltage signal is supplied to said first stage as the first and second input signals of said first stage and a clock signal having a first phase is supplied to said first stage as the pump signal of said first stage, and

wherein said first and second output signals of said first stage are supplied to said second stage as the first and second input signals of said second stage and a clock signal having a second phase, different from said first phase is supplied to said second stage as the pump signal of said second stage.

2. The voltage multiplier of claim 1 wherein said second phase is substantially 180°

from said first phase.

3. The voltage multiplier of claim 2 wherein said clock signal having a first phase is supplied as the pump signal to a plurality of alternating stages and wherein said clock signal having a second phase is supplied as the pump signal to a plurality of stages other than said alternating stages.

4. The voltage multiplier of claim 3 wherein said means for receiving and for separately pumping of each stage further comprises:

a first capacitor means having a first terminal and a second terminal with said first terminal of said first capacitor means for receiving said pump signal;

a voltage regulating means, having a first terminal and a second terminal;

said first terminal connected to said first terminal of said first transistor, and said second terminal connected to said second terminal of said first transistor;

a second transistor having a first terminal, a third terminal, a channel therebetween, and a second terminal for controlling the flow of current between the first terminal and the third terminal, and for providing said second output signal from said first terminal of said first transistor;

said first terminal of said second transistor connected to said first terminal of said first transistor;

said second terminal of said first capacitor means connected to said second terminal of said second transistor, and said second terminal of said first transistor; and

wherein said third terminal of said second transistor supplies said second output voltage.

5. The voltage multiplier of claim 4 further comprising:

a second capacitor means having a first terminal and a second terminal with said first terminal of said second capacitor means connected to said first terminal of said first capacitor means, and said second terminal of said second capacitor means connected to said first terminal of said first transistor.

6. The voltage multiplier of claim 5 wherein said first capacitor means is an MOS transistor having a first terminal, a third terminal, a channel therebetween, and a second terminal insulated from said channel, with said first terminal electrically connected to said third terminal.

7. The voltage multiplier of claim 6 wherein said second capacitor means is an MOS transistor having a first terminal, a third terminal, a channel therebetween, and a second terminal insulated from said channel, with said first terminal electrically connected to said third terminal.

8. The voltage multiplier of claim 4 wherein said voltage regulating means is a diode means.

9. The voltage multiplier of claim 8 wherein said diode means is a third MOS transistor having a first terminal, a third terminal, a channel therebetween, and a second terminal for controlling the flow of current between the first terminal and the third terminal, and wherein said second terminal is connected to the third terminal and to the second terminal of said first transistor, and said first terminal is connected to the first terminal of said first transistor.

10. The voltage multiplier of claim 1 further comprising:

a first diode means connecting said voltage signal to said first input signal; and

a second diode means connecting said voltage signal to said second input signal.

11. The voltage multiplier of claim 10 wherein each of said first and second diode means is an MOS transistor having a first terminal, a third terminal, a channel therebetween, and a second terminal for controlling the flow of current between the first terminal and the third terminal, with said second terminal connected to said third terminal, and to the voltage signal.

12. A voltage multiplier circuit comprising,

a plurality of electrically connected like stages, each stage comprising:

a first input node;

a second input node;

a first output node;

a second output node;

a pump node;

a first MOS transistor having a first terminal, a second terminal and a channel therebetween, a third terminal for controlling the flow of current between said first and second terminals;

said first terminal connected to said first input node;

said second terminal connected to said third terminal and to said second input node;

a second MOS transistor having a first terminal, a second terminal, and a channel therebetween, a third terminal for controlling the flow of current between said first and second terminals;

said first terminal connected to said first input node, said second terminal connected to said first output node and said third terminal connected to said second input node;

a third MOS transistor having a first terminal, a second terminal, and a channel therebetween, a third terminal for controlling the flow of current between said first and second terminals;

said first terminal connected to said first input node, said second terminal connected to said second output node and said third terminal connected to said second input node;

a first capacitor having a first terminal and a second terminal;

said first terminal connected to said pump node;

said second terminal connected to said second input node;

wherein said first output node of a first stage is electrically connected to the first input node of a second stage; and

said second output node of a first stage is electrically connected to the second input node of said second stage.

13. The circuit of claim 12 further comprising

a second capacitor having a first terminal and a second terminal;

said first terminal connected to said pump node;

said second terminal connected to said first input node.

14. The circuit of claim 13 wherein each of said first, second and third, MOS transistor is a N type MOS transistor.

15. The circuit of claim 13 wherein said first capacitor is an MOS transistor having a first terminal, a third terminal, a channel therebetween, and a second terminal insulated from said channel, with said first terminal electrically connected to said third terminal.