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Flip-flop for scan test chain

  • US 5,886,901 A
  • Filed: 01/07/1997
  • Issued: 03/23/1999
  • Est. Priority Date: 01/07/1997
  • Status: Expired due to Term
First Claim
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1. A method for designing an integrated circuit having a serial scan chain of modular flip-flop cells comprising the steps of:

  • defining a clock terminal for said modular flip-flop cell having a clocking event when a clock signal applied to said clock terminal changes from a first clock logic state to a second clock logic state;

    creating a data storage element for said modular flip-flop cell having a data storage input and a data storage output, wherein said data storage element transfers data from said data storage input to said data storage output at said clocking event;

    defining a test enable terminal for said modular flip-flop cell;

    defining a data input terminal for said modular flip-flop cell that is selectively coupled to said data storage input when said test enable terminal is at a first logic state;

    defining a test input terminal for said modular flip-flop cell that is selectively coupled to said data storage input when said test enable terminal is at a second logic state;

    determining a test input hold time being a minimum time that data must be stable on said test input terminal after said clocking event to ensure that the data is accurately transferred from said data storage input to said data storage output at said clocking event;

    defining a test path from said test input terminal to said data storage element;

    defining a delay element in said test path such that said test input hold time is non-positive; and

    placing a plurality of said modular flip-flop cells in an integrated circuit wherein said plurality of said modular flip-flop cells are daisy-chained together with said test input terminal of one flip-flop cell being coupled with said data output terminal of a preceding flip-flop cell.

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