Latch optimization in hardware logic emulation systems

• US 5,886,904 A
• Filed: 09/23/1996
• Issued: 03/23/1999
• Est. Priority Date: 09/23/1996
• Status: Expired due to Term

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Quickturn Design Systems Incorporated (Cadence Group)
• Inventors: Yan, Junjing, Dai, Wei-Jin
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): MOHAMED, AYNI Y
• Application Number:
  US08/718,655
• Time in Patent Office: 911 Days
• Field of Search: 364/488-491, 364/578, 395/500
• US Class Current: 703/14
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

A method for optimizing a logical design for emulation. The present invention optimzes latch-based designs by transforming them into a flip-flop based circuit. The design is analyzed to determine whether any consecutive latches are clocked by the same clock signal. If consecutive latches are clocked by the same clock signal, for example, the same phase of the same master clock, a transparency condition exists. Transparent latches are transformed into either a flip-flop/buffer/multiplexer circuit or a buffer circuit depending upon whether the latch in the logic design has an enable input. If consecutive latches in a design are clocked by different clock signals, i.e., different phases of the master clock, no transparency condition exists. Non-transparent latches are transformed into a flip-flop.

Claims

1. A method for optimizing a circuit for emulation comprising:

determining whether any latches in the circuit are transparent latches and whether any of said latches are non-transparent latches;

transforming at least one of said non-transparent latches of the circuit into a first non-latch based transformed circuit; and

transforming at least one of said transparent latches of the circuit into a second non-latch based transformed circuit

where said second non-latch based transformed circuit comprises either a first unclocked buffer if said transparent latch does not comprise an enable input or wherein said second transformed circuit comprises a flip-flop, a second unclocked buffer, and a multiplexer if said transparent latch does comprise an enable input, said inputs to said flip-flop and said second unclocked buffer comprising the input to said transparent latch, said output of said flip-flop comprising a first data input to said multiplexer, said output of said second unclocked buffer comprising a second data input to said multiplexer, said multiplexer comprising a select input having as its input the same signal input to said enable input of said transparent latch.

2. A method for optimizing a circuit for logic emulation comprising:

determining whether any latches in the circuit are transparent latches and whether any of said latches are non-transparent latches;

transforming at least one of said non-transparent latches of the circuit into a first non-latch based transformed circuit; and

transforming at least one of said transparent latches of the circuit into a second non-latch based transformed circuit

wherein said transparent latch comprises an enable input, said second non-latch based transformed circuit comprising a flip-flop, an unclocked buffer, and a multiplexer, said flip-flop comprising a data input, an enable input, a clock input and an output, said unclocked buffer comprising an input and an output, said multiplexer comprising a first data input, a second data input, and a select input, said data input to said flip-flop and said input to said buffer comprising the input to said transparent latch, said output of said flip-flop comprising said first data input to said multiplexer, said output of said buffer comprising said second data input to said multiplexer, said select input of said multiplexer comprising the same signal input to said enable input of said transparent latch.

3. A method of creating an optimized circuit for emulation from a user design, the user design comprising consecutive latches, each latch of the consecutive latches comprising a data input, an output and a clock input, the consecutive latches separated by a datapath, the datapath comprising an input feeding combinational logic and an output, the output of the datapath feeding the data input to at least one of the consecutive latches, the clock input of each latch of the consecutive latches receiving one of a plurality of clock signals, the method comprising:

determining which of the consecutive latches are clocked by identical clock signals and which of the consecutive latches are clocked by different clock signals;

labeling each of the consecutive latches clocked by identical clock signals as a transparent latch;

labeling each of the consecutive latches clocked by different clock signals as a non-transparent latch;

transforming said transparent latch into a first non-latch based transformed circuit, said first non-latch based transformed circuit comprising an input corresponding to the input of said transparent latch; and

transforming said non-transparent latch into a second non-latch based transformed circuit, said second non-latch based transformed circuit comprising an input corresponding to the input of said non-transparent latch.

4. The method of claim 3 wherein said first non-latch based transformed circuit comprises an unclocked buffer.

5. The method of claim 3 wherein said second non-latch based transformed circuit comprises a flip-flop, said flip-flop comprising a data input, a clock input, and an output, said clock input receiving an inverted one of the clock signal received by said transparent latch.

6. The method of claim 3 wherein each latch of the consecutive latches further comprise an enable input.

7. The method of claim 6 wherein said first non-latch based transformed circuit comprises a flip-flop, a buffer, and a multiplexer, said flip-flop comprising a data input, an enable input, a clock input and an output, said buffer comprising an input and an output, said multiplexer comprising a first data input, a second data input, and a select input, said data input to said flip-flop and said input to said buffer comprising the input to said transparent latch, said output of said flip-flop comprising said first data input to said multiplexer, said output of said buffer comprising said second data input to said multiplexer, said select input of said multiplexer comprising the same signal input to said enable input of said transparent latch, and said clock input of said flip-flip receiving an inverted one of the clock signal received by said transparent latch.

8. The method of claim 7 further comprising the step of placing an output of a logic gate onto said enable input of said flip-flop, said logic gate having as a first input the same signal input to said enable input of said transparent latch, said logic gate having said clock input of said transparent latch as a second input, said clock input being inverted.

9. The method of claim 6 wherein said second non-latch based transformed circuit comprises a flip-flop, said flip-flop comprising a data input, an enable input, a clock input and an output.

10. The method of claim 9 further comprising the step of placing an output of a logic gate onto said enable input of said flip-flop, said logic gate having as a first input the same signal input to said enable input of said non-transparent latch, said logic gate having said clock input of said non-transparent latch as a second input, said clock input being inverted.

11. A method for optimizing a circuit for logic emulation comprising:

determining whether any latches in the circuit are transparent latches and whether any of said latches are non-transparent latches;

transforming at least one of said non-transparent latches of the circuit into a first transformed circuit; and

transforming at least one of said transparent latches of the circuit into a second transformed circuit, wherein said second transformed circuit comprises either a first unclocked buffer if said transparent latch does not comprise an enable input or wherein said second transformed circuit comprises a flip-flop, a second unclocked buffer, and a multiplexer if said transparent latch does comprise an enable input, said inputs to said flip-flop and said second unclocked buffer comprising the input to said transparent latch, said output of said flip-flop comprising a first data input to said multiplexer, said output of said second unclocked buffer comprising a second data input to said multiplexer, said multiplexer comprising a select input having as its input the same signal input to said enable input of said transparent latch.

12. A method for optimizing a circuit for logic emulation comprising:

determining whether any latches in the circuit are transparent latches and whether any of said latches are non-transparent latches;

transforming at least one of said non-transparent latches of the circuit into a first transformed circuit;

transforming at least one of said transparent latches of the circuit into a second transformed circuit; and

said transparent latch comprising an enable input, said second transformed circuit comprising a flip-flop, an unclocked buffer, and a multiplexer, said flip-flop comprising a data input, an enable input, a clock input and an output, said unclocked buffer comprising an input and an output, said multiplexer comprising a first data input, a second data input, and a select input, said data input to said flip-flop and said input to said buffer comprising the input to said transparent latch, said output of said flip-flop comprising said first data input to said multiplexer, said output of said buffer comprising said second data input to said multiplexer, said select input of said multiplexer comprising the same signal input to said enable input of said transparent latch.

13. A method of creating an optimized circuit for emulation from a user design, the user design comprising consecutive latches, each latch of the consecutive latches comprising a data input, an output and a clock input, the consecutive latches separated by a datapath, the datapath comprising an input feeding combinational logic and an output, the output of the datapath feeding the data input to at least one of the consecutive latches, the clock input of each latch of the consecutive latches receiving one of a plurality of clock signals, the method comprising:

determining which of the consecutive latches are clocked by identical clock signals and which of the consecutive latches are clocked by different clock signals;

labeling each of the consecutive latches clocked by identical clock signals as a transparent latch;

labeling each of the consecutive latches clocked by different clock signals as a non-transparent latch;

transforming said transparent latch into a first transformed circuit, said first transformed circuit comprising an input corresponding to the input of said transparent latch; and

transforming said non-transparent latch into a second transformed circuit, said second transformed circuit comprising an input corresponding to the input of said non-transparent latch, said second transformed circuit further comprising a flip-flop, said flip-flop comprising a data input, a clock input, and an output, said clock input receiving an inverted one of the clock signal received by said transparent latch.

14. A method of creating an optimized circuit for emulation from a user design, the user design comprising consecutive latches, each latch of the consecutive latches comprising a data input, an output and a clock input, the consecutive latches separated by a datapath, the datapath comprising an input feeding combinational logic and an output, the output of the datapath feeding the data input to at least one of the consecutive latches, the clock input of each latch of the consecutive latches receiving one of a plurality of clock signals, the method comprising:

determining which of the consecutive latches are clocked by identical clock signals and which of the consecutive latches are clocked by different clock signals;

labeling each of the consecutive latches clocked by identical clock signals as a transparent latch;

labeling each of the consecutive latches clocked by different clock signals as a non-transparent latch;

transforming said transparent latch into a first transformed circuit, said first transformed circuit comprising an input corresponding to the input of said transparent latch;

transforming said non-transparent latch into a second transformed circuit, said second transformed circuit comprising an input corresponding to the input of said non-transparent latch; and

wherein each latch of the consecutive latches further comprise an enable input, said first transformed circuit further comprising a flip-flop, a buffer, and a multiplexer, said flip-flop comprising a data input, an enable input, a clock input and an output, said buffer comprising an input and an output, said multiplexer comprising a first data input, a second data input, and a select input, said data input to said flip-flop and said input to said buffer comprising the input to said transparent latch, said output of said flip-flop comprising said first data input to said multiplexer, said output of said buffer comprising said second data input to said multiplexer, said select input of said multiplexer comprising the same signal input to said enable input of said transparent latch, and said clock input of said flip-flip receiving an inverted one of the clock signal received by said transparent latch.

15. The method of claim 14 further comprising the step of placing an output of a logic gate onto said enable input of said flip-flop, said logic gate having as a first input the same signal input to said enable input of said transparent latch, said logic gate having said clock input of said transparent latch as a second input, said clock input being inverted.

16. A method of creating an optimized circuit for emulation from a user design, the user design comprising consecutive latches, each latch of the consecutive latches comprising a data input, an output and a clock input, the consecutive latches separated by a datapath, the datapath comprising an input feeding combinational logic and an output, the output of the datapath feeding the data input to at least one of the consecutive latches, the clock input of each latch of the consecutive latches receiving one of a plurality of clock signals, the method comprising:

determining which of the consecutive latches are clocked by identical clock signals and which of the consecutive latches are clocked by different clock signals;

labeling each of the consecutive latches clocked by identical clock signals as a transparent latch;

labeling each of the consecutive latches clocked by different clock signals as a non-transparent latch;

transforming said transparent latch into a first transformed circuit, said first transformed circuit comprising an input corresponding to the input of said transparent latch;

transforming said non-transparent latch into a second transformed circuit, said second transformed circuit comprising an input corresponding to the input of said non-transparent latch, said second transformed circuit comprising a flip-flop, said flip-flop comprising a data input, an enable input, a clock input and an output; and

placing an output of a logic gate onto said enable input of said flip-flop, said logic gate having as a first input the same signal input to said enable input of said non-transparent latch, said logic gate having said clock input of said non-transparent latch as a second input, said clock input being inverted.