Boundary scan architecture analog extension with direct connections

• US 5,887,001 A
• Filed: 10/08/1997
• Issued: 03/23/1999
• Est. Priority Date: 12/13/1995
• Status: Expired due to Term

• Current Assignee: Bull HN Information Systems Incorporated (Atos SE)
• Original Assignee: Bull HN Information Systems Incorporated (Atos SE)
• Inventors: Russell, Robert J.
• Primary Examiner(s): Nguyen, Hoa T.
• Application Number:
  US08/946,952
• Time in Patent Office: 531 Days
• Field of Search: 371/22.31, 371/22.1, 371/22.5, 371/22.6, 364/579
• US Class Current: 714/726
• CPC Class Codes: G01R 31/2815 Functional tests, e.g. boundary scans, using the normal I/O contacts contacting devices G01R31/2808; testing digital circuits G01R31/317, G06F11/00
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals
• CPC Class Codes: G01R 31/318555 Control logic

Abstract

A method and apparatus provides an analog mode of operation of a standard test access bus interface based on a standard boundary scan architecture which is limited to use of digital signals. Circuits are included in the interface which enable the sharing of control paths at separate time intervals defined under instruction control for processing analog and digital signals thereby providing a hybrid capability without any increase in the number of lines required by the interface.

Claims

1. A method of extending the capability of a standard boundary scan interface of an integrated circuit (IC) to process both digital and analog signals, said interface having a digital data input (TDI) terminal, a digital data output (TDO) terminal, a test mode select (TMS) terminal, a test clock (TCK) terminal and a digital control section including a controller for defining a plurality of operational states for said interface and for generating in response to instructions applied to the interface, control signals used to control testing of circuits associated with the IC wherein the IC can be used in a system containing a number of ICs serially connected to form a boundary scan chain and said method comprising:

(a) extending the interface by connecting a control switching circuit included within the digital control section between the controller and the TMS and TCK terminals for properly configuring TMS and TCK terminals as inputs to the controller for operating the interface to pass signals in a first instance and to pass analog signals in a second instance so as to operate the interface in both digital and analog modes;

(b) next, extending the interface by connecting a phase control counter circuit included within the digital control section to the TDI terminal to receive externally generated digital control signals therefrom during analog mode of operation for sequencing the counter circuit through a number of states for producing signals defining predetermined phases of operation and to the control switching circuit for the configuring of the TMS and TCK terminals for operating the interface in either analog or digital mode according to the predetermined phases of operation;

(c) further extending the interface by connecting analog control means to the TDI terminal and to the phase control counter circuit for receiving digital control signals and the signals defining the predetermined phases of operation respectively therefrom; and

,

(d) connecting the analog control means to the controller of the digital control section for operating the analog control means in response to said instructions and to be responsive to a predetermined data bit pattern received by the analog control means through the TDI terminal prior to analog activity, the analog control means producing output signals to be used for enabling the transfer of analog signals through the TCK and TMS terminals of the IC for carrying out analog testing in conjunction with the extended interface during predetermined phases of operation defined by the phase control counter circuit.

2. The method of claim 1 wherein the digital control section includes a plurality of standard registers connected to the controller and a direct register circuit and wherein step (d) of said method further comprises:

(e) generating signals for connecting the TDI terminal to the TDO terminal through the direct register circuit for directly transferring digital signals applied to the TDI terminal to the TDO terminal for controlling the sequencing of phases in the IC.

3. The method of claim 2 wherein the IC further includes a number of elements and said method further includes:

(f) connecting the TMS terminal to a first number of test and control points within the circuits of the IC through first analog switching circuit means included in the analog control means for extending the interface, for establishing at least one first circuit path;

(g) connecting the TCK terminal to a second number of test and control points within the circuits through second analog switching circuit means included in the analog control means for extending the interface, for establishing at least one second circuit path;

(h) connecting decode control means included within the analog control means for extending the interface, to each of the first and second analog switching means; and

,

(i) the decode control means when enabled by certain bits of the predetermined data bit pattern applying enabling signals for connecting predetermined ones of the analog switching circuit means to provide first and second circuit paths to selected ones of said test and control points for passing and monitoring analog signals for testing the elements connected to the test and control points.

4. The method of claim 3 wherein the operations of step (i) are carried out during different ones of the predetermined number of phases.

5. The method of claim 3 wherein the elements connected to the test and control points are included as part of the circuits of the IC.

6. The method of claim 3 wherein said method further includes:

(j) connecting a number of voltage reference potential points to a third number of test and control points within the circuits through third analog switching circuit means included in the analog control means for extending the interface, for applying reference voltage potentials to the third number of test and control points when said interface is operating in the analog mode.

7. The method of claim 3 wherein each of said first, second and third analog switching means includes a number of analog switches and said digital control section further including a plurality of registers connected between said TDI and TDO terminals, one of said plurality of registers corresponding to an instruction register for storing said instructions applied to said interface, said method further including:

(k) connecting another one of said plurality of registers as an analog control register included within the analog control means for storing the predetermined data bit pattern loaded into said analog control register by the digital control section in response to decoding of a predetermined type of instruction; and

,

(l) coding said predetermined data bit pattern to specify connect and disconnect states for said number of analog switches in said first, second and third analog switching means for establishing said first and second circuit paths.

8. The method of claim 7 wherein said number of the number of analog switches in the first and second analog switching means is related to the number of test and control points and is arranged to form a matrix.

9. The method of claim 3 wherein the IC has a number of terminals used for interconnecting the IC to a further IC and wherein a number of the elements are located external to the IC and connected to the number of terminals of the IC.

10. The method of claim 1 wherein in step (b) the control switching circuit is configured in a manner which inhibits the TMS and TCK terminals from applying signals to the control state machine during the predetermined phases of operation defined by the phase counter circuit.

11. Apparatus for extending the capability of a standard boundary scan interface of an integrated circuit (IC) to process both digital and analog signals, said interface having a digital data input (TDI) terminal, a digital data output (TDO) terminal, a test mode select (TMS) terminal, a test clock (TCK) terminal and a digital control section including a controller for defining a plurality of operational states for said interface and for generating in response to instructions applied to the interface, control signals used to control testing of circuits associated with the IC wherein the IC connects to a further IC and said apparatus comprising:

a control switching circuit means included within the digital control section having a number of inputs and outputs, first and second inputs being connected to the TMS and TCK terminals and the outputs being connected to the controller, the control switching circuit means properly configuring TMS and TCK terminals as inputs to the controller for operating the interface to pass digital signals in a first instance and to pass analog signals in a second instance so as to operate the interface in both digital and analog modes;

a phase control counter circuit included within the digital control section having a number of inputs and a number of outputs, a first input being connected to the TDI terminal for receiving externally generated digital control signals during analog mode of operation for sequencing the phase control counter circuit through a number of states for producing signals defining predetermined phases of operation, a second input being connected to the control state machine and different ones of the outputs being connected to other inputs of the control switching circuit means; and

analog control means having a number of inputs and a number of outputs, one of the inputs being connected to the TDI terminal, the remaining of the inputs being connected to the phase control counter circuit and to receive signals from the controller of the digital control section for operating in response to said instructions, the analog control means in response to the signals corresponding to a data bit pattern through the TDI terminal prior to analog activity, generating output signals to be used in transferring analog signals through the TCK and TMS terminals of IC for analog testing with the extended interface during the predetermined phases of operation.

12. The apparatus of claim 11 wherein the digital control section includes a plurality of standard registers connected to the controller and a direct register circuit, a multiplexer circuit having a number of inputs and an output connected to the TDO terminal of the IC, each register and direct register circuit having a serial input and a serial output, the serial input of each register and direct register circuit being connected to the TDI terminal and the serial output of each register and direct register circuit being connected to a different one of the multiplexer inputs, the controller of the digital control section generating signals for connecting the TDI terminal to the TDO terminal through the direct register circuit for directly transferring digital signals applied to the TDI terminal to the TDO terminal for controlling the sequencing of phases in the further IC.

13. The apparatus of claim 12 wherein the IC further includes a number of elements and wherein the analog control means further includes:

first analog switching circuit means connecting the TMS terminal to a first number of test and control points within the circuits of the IC for establishing at least one first circuit path;

second analog switching circuit means connecting the TCK terminal to a second number of test and control points within the circuits of the IC for establishing at least one second circuit path; and

,

decode control means connected to each of the first and second analog switching means;

the decode control means when enabled by certain bits of the predetermined bit pattern, applying enabling signals for connecting predetermined ones of the analog switching circuit means to provide first and second circuit paths to selected ones of said test and control points for passing and monitoring analog signals for testing the elements connected to the test and control points.

14. The apparatus of claim 13 wherein the IC has a number of terminals used for interconnecting the IC to the further IC and wherein the number of elements are located external to the IC and connect to the number of terminals of said IC.

15. The apparatus of claim 12 wherein said analog control means further includes:

third analog switching circuit means connecting a number of voltage reference potential points to a third number of test and control points within the circuits for applying reference voltage potentials to the third number of test and control points when said interface is operating in said analog mode.

16. The apparatus of claim 12 wherein each of said first and analog switching means includes a number of analog switches and wherein one of the standard registers corresponds to an instruction register for storing instructions applied to said interface.

17. The apparatus of claim 15 wherein another one of the number of standard registers is an analog control register included within the analog control means for storing the predetermined data bit pattern loaded into said analog control register by the digital control section in response to decoding of a predetermined type of instruction, said data bit pattern being coded to specify connect and disconnect states for said number of analog switches in said first and second analog switching means for establishing said first and second circuit paths.

18. The apparatus of claim 16 wherein said number of said analog switches in said first and second analog switching means is related to the number of test and control points, said number of analog switches of said first and second analog switching means being arranged to form a matrix.

19. A method of extending the capability of a standard boundary scan interface of an integrated circuit (IC) to process both digital and analog signals, said interface having a digital data input (TDI) terminal, a digital data output (TDO) terminal, a test mode select (TMS) terminal, a test clock (TCK) terminal and a digital control section including a controller for defining a plurality of operational states for said interface and for generating control signals in response to instructions applied to the interface and a plurality of standard control registers connected to the controller and a direct register circuit, the control signals being used to control the boundary scan testing of circuits associated with the IC, the IC being serially connected to a further IC through the TDI and TDO terminals for testing and said method comprising:

(a) extending the interface by connecting a control switching circuit included within the digital control section between the controller and the TMS and TCK terminals for properly configuring TMS and TCK terminals as inputs to the controller for operating the interface to pass digital signals in a first instance and analog signals in a second instance so as to operate the interface in both digital and analog modes;

(b) further extending the interface by connecting a phase control counter circuit included within the digital control section to the TDI terminal to receive externally generated digital control signals during analog mode of operation for sequencing the phase control counter circuit through a number of states for producing signals defining predetermined phases of operation and to the control switching circuit for the configuring of the TMS and TCK terminals for operating the interface in either analog or digital mode according to the predetermined phases of operation; and

,

(c) connecting the TDI terminal to the TDO terminal through the direct register circuit in response to control signals from the controller for transferring the externally generated digital control signals applied to the TDI terminal to the TDO terminal of the further IC for controlling the sequencing of the predetermined phases of operation in the further IC.

20. A method of extending the capability of a standard boundary scan interface of an integrated circuit (IC) to process both digital and analog signals, the interface having a digital data input (TDI) terminal, a digital data output (TDO) terminal, a test mode select (TMS) input terminal, a test clock (TCK) terminal and a digital control section including a controller for defining a plurality of operational states for the interface and for generating in response to instructions applied to the interface, control signals used to control the testing of elements connected to test and control points of the IC, the IC being serially connected through the TDI and TDO terminals to a further IC for boundary scan testing, the method comprising:

(a) extending the interface by connecting control switching circuit means included within the digital control section between the controller and the TMS and TCK terminals for properly configuring TMS and TCK terminals as inputs to the controller for operating the interface in both analog and digital modes;

(b) next, extending the interface by connecting a phase control counter circuit included within the digital control section to the TDI terminal to receive externally generated digital control signals therefrom during analog mode of operation for sequencing the phase control counter circuit through a number of states for producing signals defining predetermined phases of operation and to the control switching circuit means for the configuring of the TMS and TCK terminals for operating the interface in either analog or digital mode based on the predetermined phases of operation;

(c) further extending the interface by connecting analog control means to the TDI terminal and to the phase control counter circuit for receiving digital control signals and the signals defining the predetermined phases of operation respectively therefrom;

(d) connecting the analog control means to the controller for operating in response to said instructions and a predetermined data bit pattern received through the TDI terminal prior to analog activity;

(e) connecting the TMS terminal to a first number of the test and control points of the IC through first analog switching circuit means included in the analog control means for extending the interface, for establishing at least one first circuit path;

(f) connecting the TCK terminal to a second number of the test and control points of the IC through second analog switching circuit means included in the analog control means for extending the interface, for establishing at least one second circuit path;

(g) connecting decode control means included within the analog control means included for extending the interface, to each of the first and second analog switching means; and

,

(h) the decode control means when enabled by certain bits of the predetermined data bit pattern applying enabling signals for connecting predetermined ones of the analog switching circuit means to provide first and second circuit paths to selected ones of said test and control points for passing and monitoring analog signals received from the TMS and TCK terminals for testing the elements connected to the test and control points.

21. The method of claim 20 wherein the IC has a number of terminals used for interconnecting the IC to the further IC, a number of the elements being located external to the IC and being connected to the number of terminals and wherein the further IC includes the extended interface for conducting analog testing of the elements located external to the IC.