Symmetric multiprocessing computer with non-uniform memory access architecture

• US 5,887,146 A
• Filed: 08/12/1996
• Issued: 03/23/1999
• Est. Priority Date: 08/14/1995
• Status: Expired due to Term

• Current Assignee: Data General Corp. (Dell Technologies Inc.)
• Original Assignee: Data General Corp. (Dell Technologies Inc.)
• Inventors: Guyer, James M., Sporer, Michael, Cox, Joseph, Gelinas, Robert G., Roux, Phil J., Sherman, Art A., Keating, David L., Yeung, Simon N., Radogna, Tom V., Hunt, Michael F., Baxter, William F., Gillott, Barry E., Truebenbach, Liz M., Pike, Rob J., Kimmell, Jeff S., Tucker, Doug J., Weiler, Pat J., Huck, Dan R., Heyda, Andrea, Valentine, Rob P.
• Primary Examiner(s): PANCHOLI, JIGAR K
• Application Number:
  US08/695,556
• Time in Patent Office: 953 Days
• Field of Search: 395/284, 395/306, 395/312, 395/403, 395/445, 395/473, 395/553
• US Class Current: 710/104
• CPC Class Codes: G06F 11/22 Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
• CPC Class Codes: G06F 11/2289 by configuration test
• CPC Class Codes: G06F 11/267 Reconfiguring circuits for testing, e.g. LSSD, partitioning
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 13/36 for access to common bus or bus system
• CPC Class Codes: G06F 2212/2542 Non-uniform memory access [NUMA] architecture

Abstract

A very fast, memory efficient, highly expandable, highly efficient CCNUMA processing system based on a hardware architecture that minimizes system bus contention, maximizes processing forward progress by maintaining strong ordering and avoiding retries, and implements a full-map directory structure cache coherency protocol. A Cache Coherent Non-Uniform Memory Access (CCNUMA) architecture is implemented in a system comprising a plurality of integrated modules each consisting of a motherboard and two daughterboards. The daughterboards, which plug into the motherboard, each contain two Job Processors (JPs), cache memory, and input/output (I/O) capabilities. Located directly on the motherboard are additional integrated I/O capabilities in the form of two Small Computer System Interfaces (SCSI) and one Local Area Network (LAN) interface. The motherboard includes main memory, a memory controller (MC) and directory DRAMs for cache coherency. The motherboard also includes GTL backpanel interface logic, system clock generation and distribution logic, and local resources including a micro-controller for system initialization. A crossbar switch connects the various logic blocks together. A fully loaded motherboard contains 2 JP daughterboards, two PCI expansion boards, and up to 512 MB of main memory. Each daughterboard contains two 50 MHz Motorola 88110 JP complexes, having an associated 88410 cache controller and 1 MB Level 2 Cache. A single 16 MB third level write-through cache is also provided and is controlled by a third level cache controller.

Claims

1. A scalable multiprocessor computer system, comprising:

a backplane, including at least one backplane communication bus;

a plurality of motherboards, detachably connected to said backplane;

each motherboard interfacing to said at least one backplane communication bus, each of said plurality of motherboards including;

at least one backplane communication bus interface mechanism interfacing at least one of said plurality of motherboards to said at least one backplane communication bus;

a motherboard communication bus comprising a first segment that is selectably interfaceable to said at least one backplane communication bus and at least one second segment, said motherboard communication bus including a crossbar register switch selectably interconnecting said at least one second segment of said motherboard communication bus to said first segment;

a motherboard communication bus request arbitration mechanism arbitrating requests from said plurality of motherboards for access to said first segment and said at least one second segment of said motherboard communication bus by selected ones of said plurality of motherboards;

a memory system including main memory distributed among said plurality of motherboards, directory memory for maintaining main memory coherency with caches on other motherboards, and a memory controller module for accessing said main memory and directory memory and interfacing to said motherboard communication bus; and

at least one daughterboard, detachably connected to said motherboard and interfacing to said motherboard communication bus, said at least one daughterboard further including;

a motherboard communication bus interface module, for interfacing said at least one daughterboard to said motherboard communication bus and a local bus on said daughterboard; and

at least one cache memory system including cache memory and a cache controller module maintaining said cache memory for a processor of said scalable multiprocessor computer system.

2. The scalable multiprocessor computer system of claim 1 wherein said main memory is contiguously addressable across said plurality of motherboards.

3. The scalable multiprocessor computer system of claim 1 wherein said backplane includes four backplane communication busses, and each of said plurality of motherboards includes four backplane communication bus interface modules.

4. The scalable multiprocessor computer system of claim 1 wherein one of said plurality of motherboards is selected to provide a system clock signal for all motherboards.

5. The scalable multiprocessor computer system of claim 4 wherein a second one of said plurality of motherboards is selected to provide a backup system clock signal for all motherboards.

6. The scalable multiprocessor computer system of claim 1 wherein each of said plurality of motherboards includes a peripheral interface module, said peripheral interface module interfacing to said motherboard communication bus, and to at least one peripheral device.

7. The scalable multiprocessor computer system of claim 6 wherein said at least one peripheral device is one of a local area network (LAN) device, a small computer system interface (SCSI) device or an expansion card device.

8. The scalable multiprocessor computer system of claim 1 wherein said at least one daughterboard includes two processor modules.

9. The scalable multiprocessor computer system of claim 8 wherein said at least one cache memory system on said on said at least one daughterboard provides a cache for said two processor modules.

10. A scalable distributed memory multiprocessor computer system including a backplane comprising a plurality of identical independent backplane buses, said backplane providing communication paths for a plurality of motherboards, each of said motherboards including at least one processor with a local cache memory, a motherboard communications bus, a motherboard communications bus to backplane interface module, and a memory system, wherein:

said motherboard communications bus to backplane interface module includes three input queues of high, medium, and low priority, and packets sent on said backplane to a motherboard are placed in one of said input queues depending on the priority of each packet;

all packets to the same cache line use the same one of said plurality of identical independent backplane buses;

high priority packets are always accepted into said memory system on a motherboard without needing to retry;

medium priority packets received from said plurality of identical independent backplane buses are granted onto a motherboard communication bus in the order in which said medium priority packages are received from said plurality of identical independent backplane buses;

packets for cache-inhibited reads, cache-inhibited writes, and cache-inhibited write unlocks are ordered with previous invalidate command and read invalidate reply packets previously inserted in said medium priority input queue;

packets to be received by more than one motherboard will arrive to each motherboard simultaneously;

all copyback invalidate commands and copyback commands are sent out on said backplane to a receiving motherboard;

all invalidate copybacks are sent out on said backplane to a receiving motherboard; and

a motherboard will retry any local resource requests while said medium input queue of said motherboard communications bus to backplane interface module contains any read invalidate reply, invalidate command, or copyback invalidate command packets.

11. The scalable distributed memory multiprocessor computer system of claim 10, wherein:

packets of low priority include cache-inhibited reads, cache inhibited writes, cache-inhibited write unlock and write-through;

packets of medium priority include invalidate commands, read invalidate replies, and copyback invalidate commands; and

packets of high priority include copyback replies, copyback invalidate replies, and writebacks.

12. A scalable multiprocessor computer system, comprising:

a backplane, including at least one backplane communication bus;

a plurality of motherboards, detachably connected to said backplane;

each motherboard interfacing to said at least one backplane communication bus, each of said plurality of motherboards including;

at least one backplane communication bus interface mechanism interfacing at least one of said plurality of motherboards to said at least one backplane communication bus;

a motherboard communication bus comprising a first segment that is selectably interfaceable to said at least one backplane communication bus and a plurality of second segments, said motherboard communication bus including means for selectably interconnecting one of said plurality of second segments of said motherboard communication bus to said first segment;

an arbitration means for arbitrating requests from said plurality of motherboards for access to said first segment and said one of said plurality of second segments of said motherboard communication bus by selected ones of said plurality of motherboards;

a memory system including main memory distributed among said plurality of motherboards, directory means for maintaining main memory coherency with caches on other motherboards, and a memory controller means for accessing said main memory and directory memory and interfacing to said motherboard communication bus; and

at least one daughterboard, detachably connected to said motherboard and interfacing to said motherboard communication bus, said at least one daughterboard further including;

a motherboard communication bus interface means for interfacing said at least one daughterboard to said motherboard communication bus and a local bus on said daughterboard; and

at least one cache memory system including cache memory and a cache controller means for maintaining said cache memory for a processor of said scalable multiprocessor computer system.

13. A crossbar register switch for use in a scaleable multiprocessor computer system including at least one backplane communication bus, and a plurality of motherboards interfaced to said at least one backplane communication bus, each of said plurality of motherboards including a motherboard communication bus comprising a first segment that is selectably interfaceable to said at least one backplane communication bus and a plurality of second segments;

said crossbar register switch comprising;

an interface to said first segment of said motherboard communication bus;

a plurality of bidirectional ports, said bidirectional ports interfacing to said plurality of second segments of said motherboard communication bus;

a motherboard communication bus request arbitration mechanism arbitrating requests from said plurality of motherboards for access to said first segment and to one of said plurality of second segments of said motherboard communication bus by selected ones of said plurality of motherboards;

wherein said crossbar register switch selectably interconnects said first segment of said motherboard communication bus to one of said second segments of said motherboard communication bus through a bidirectional port based arbitration by said motherboard communication bus request arbitration mechanism.

14. The crossbar register switch of claim 13 wherein said scaleable multiprocessor computer system includes a memory system including main memory distributed among said plurality of motherboards, directory memory for maintaining main memory coherency with caches on other motherboards, and a memory controller module for accessing said main memory and directory memory and interfacing to said motherboard communication bus.

15. The crossbar register switch of claim 13 wherein said crossbar register switch is implemented in a plurality of identical integrated circuit modules.

16. In a scalable distributed memory multiprocessor computer system including a backplane comprising a plurality of identical independent backplane buses, said backplane providing communication paths for a plurality of motherboards, each of said motherboards including at least one processor with a local cache memory, a motherboard communications bus, a motherboard communications bus to backplane interface module, and a memory system;

a method for communicating between said motherboard communication bus and said backplane busses comprising;

providing three input queues of high, medium, and low priority;

designating which input queue to place a packet sent on said backplane to a motherboard;

guaranteeing that high priority packets will be received at the destination;

allowing packets to be received by more than one motherboard to arrive to each motherboard simultaneously;

ordering packets in said medium priority queue so that any medium priority packets which involve snoops or invalidations are ordered with previous invalidate command and read invalidate reply packets previously inserted in said medium priority queue across all backplane busses; and

sending any local memory requests out onto one of said backplane busses and into said while said medium priority queue of said motherboard communications bus to backplane interface module contains any read invalidate reply, invalidate command, or copyback invalidate command packets.

17. The method of claim 16, further including the steps of:

designating packets of low priority to include requests;

designating packets of medium priority to include replies and snoops; and

designating packets of high priority to include copyback replies and writebacks.

18. The method of claim 16, further including the steps of:

designating packets of low priority to include cache-inhibited reads, cache inhibited writes, cache-inhibited write unlock and write-through;

designating packets of medium priority to include invalidate commands, read invalidate replies, and copyback invalidate commands; and

designating packets of high priority to include copyback replies, copyback invalidate replies, and writebacks.