Method and system in a data processing system for loading and storing vectors in a plurality of modes

• US 5,887,183 A
• Filed: 01/04/1995
• Issued: 03/23/1999
• Est. Priority Date: 01/04/1995
• Status: Expired due to Fees

• Current Assignee: Intellectual Property I KFT
• Original Assignee: International Business Machines Corporation
• Inventors: Lyon, Terry L., Groves, Randall Dean, Olsson, Brett, Johnson, Mark A., Agarwal, Ramesh Chandra, Shearer, James B., Gustavson, Fred G.
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US08/368,173
• Time in Patent Office: 1,539 Days
• Field of Search: 395/800, 395/800.02, 395/800.14, 395/800.17, 395/800.07, 395/800.04
• US Class Current: 712/2
• CPC Class Codes: G06F 15/8092 Array of vector units
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/3455 using stride
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]

Abstract

A vector having a plurality of elements is stored in an input storage area, wherein the vector elements are stored in a first pattern. Thereafter, the elements are transferred, in a first order, from the input storage area into a vector register interface unit. From the vector register interface unit, the elements are transferred to an output storage area and stored in addressable locations in one of a plurality of preselected patterns. The input storage area may be implemented with cache memory or a register array. The output storage area may be implemented with a cache memory or a register array. The first pattern in the input storage area may include alternating real and imaginary elements. The plurality of preselected patterns may include a reversed order pattern, or a separation of real and imaginary elements into two vector registers.

Claims

1. A method in a vector processing system for transferring vectors having a plurality of elements between a register array having N sequentially numbered rows of addressable registers and M sequentially numbered columns of addressable registers for storing said plurality of elements and a memory having addressable storage locations, said method comprising the steps of:

storing a vector having a plurality of sequentially numbered elements in said register array, said plurality of sequentially numbered elements including both real elements and imaginary elements, wherein said real elements are stored in sequential order in a first one of said M columns and said imaginary elements are stored in sequential order in a second one of said M columns for transfer to a vector register interface unit;

in response to receipt of at least one address at said register array, transferring, in a first order, said plurality of elements from addressable registers in said register array specified by said at least one address into said vector register interface unit, said transferring step including the step of transferring, in a first order, a plurality of sequentially numbered elements from a selected one of said N rows in said register array into said vector register interface unit; and

transferring said plurality of sequentially numbered elements from said vector register interface unit to said memory such that said plurality of elements are stored in said addressable locations in said memory in one of a plurality of preselected patterns, wherein said step of transferring said plurality of elements from said vector register interface unit to said memory includes the step of transferring said plurality of real and imaginary elements from said vector register interface unit to sequentially numbered locations in said memory such that said real and imaginary elements are alternately stored in said sequentially numbered locations in said memory.

2. A vector processing system, comprising:

a register array having N sequentially numbered rows of addressable registers and M sequentially numbered columns of addressable registers for storing a vector having a plurality of sequentially numbered elements including both real elements and imaginary elements, wherein said real elements are stored in sequential order in a first one of said M columns and said imaginary elements are stored in sequential order in a second one of said M columns for transfer to said vector register interface unit, wherein said register array outputs said plurality of sequentially numbered elements in response to receipt of at least one address specifying said addressable registers that store said plurality of elements;

a memory having addressable storage locations; and

a vector register interface unit coupled between said register array and said memory, wherein responsive to receipt of said plurality of sequentially numbered elements from said register array, said vector register interface unit transfers, in a first order, said plurality of sequentially numbered elements into said memory such that said plurality of elements area are stored in said addressable locations of said memory in one of a plurality of preselected patterns.

3. The vector processing system of claim 2, and further comprising a vector execution unit for processing said plurality of elements forming said vector, wherein said register array is within said vector execution unit.