Single chip network adapter apparatus

• US 5,887,187 A
• Filed: 04/14/1997
• Issued: 03/23/1999
• Est. Priority Date: 10/20/1993
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Desai, Sanjay, Rostoker, Michael D., Daane, John P., Stelliga, D. Tony
• Primary Examiner(s): Rinehart, Mark H.
• Application Number:
  US08/839,464
• Time in Patent Office: 708 Days
• Field of Search: 395/800.28, 395/800.29, 395/800.3, 395/200.3, 395/200.8, 395/200.63, 395/200.76, 395/200.81, 395/309, 395/311, 395/872
• US Class Current: 712/29
• CPC Class Codes: G06F 13/128 for dedicated transfers to a network for protocol converters G06F13/387
• CPC Class Codes: H04L 2012/5616 Terminal equipment, e.g. codecs, synch.
• CPC Class Codes: H04L 2012/5638 Services, e.g. multimedia, GOS, QOS
• CPC Class Codes: H04L 2012/5653 using the ATM adaptation layer [AAL]
• CPC Class Codes: H04L 45/745 Address table lookup; Address filtering
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9057 Arrangements for supporting packet reassembly or resequencing
• CPC Class Codes: H04L 49/9063 Intermediate storage in different physical parts of a node or terminal
• CPC Class Codes: H04L 49/9073 Early interruption upon arrival of a fraction of a packet
• CPC Class Codes: H04L 49/9078 using an external memory or storage device
• CPC Class Codes: H04N 19/61 in combination with predictive coding

Abstract

A single chip network adapter apparatus has each component disposed on a single semiconductor chip. The network adapter includes a host interface circuit which is adapted for connection directly to a host system bus. The host interface circuit sends information to and receives information form the host system bus, and has random access memory coupled thereto. A processor is coupled to the random access memory and formats information received from the host system bus to a network protocol format. The processor also converts information received in a network protocol format to a form suitable for the host system bus. A network interface circuit is coupled to the random access memory and is adapted for connection directly to a network. The network interface circuit sends information formatted by the processor to the network and receives information to be converted by the processor from the network.

Claims

1. A single chip network adapter apparatus, comprising:

a host interface circuit adapted for connection directly to a host system bus, the host interface circuit being operative to send information to and receive information from the host system bus;

random access memory (RAM) for storing information in a network protocol format and in a host computer format, said RAM coupled to the host interface circuit;

a microprocessor coupled to the random access memory for formatting information received from the host system bus to a network protocol format, and for converting information received in a network protocol format to said host computer format; and

a network interface circuit coupled to the random access memory and adapted for connection directly to a network, the network interface circuit being operative to send information formatted by the processor to the network and to receive information to be converted by the processor from the network;

the host interface circuit, the random access memory, the processor, and the network interface circuit being disposed on a single chip.

2. The single chip network apparatus according to claim 1, further comprising:

a direct memory access (DMA) circuit coupled to the host interface circuit for controlling the transfer of information to and from an external memory coupled to the host system bus;

the DMA circuit being disposed on said single chip.

3. The single chip network apparatus according to claim 2, wherein the host interface circuit is adapted for connection directly to a parallel cell interface (PCI) bus.

4. The single chip network apparatus according to claim 3, wherein the network interface circuit comprises asynchronous transfer mode (ATM) segmentation and assembly circuity for use with an ATM network protocol.

5. The single chip network apparatus according to claim 4, wherein the network interface circuit further comprises ATM transmission convergence circuits.

6. The single chip network apparatus according to claim 3, wherein the network interface circuit further comprises synchronous optical network/synchronous digital hierarchy (SONET/SDH) framers for interfacing to a network.

7. The single chip network apparatus according to claim 3, wherein the network interface circuit further comprises a physical layer circuit adapted for connection directly to the network.

17. The single chip network adapter apparatus according to claim 2, wherein the network interface circuit includes a physical-layer medium dependent (PMDI) circuit on said single chip.

18. The single chip network adapter apparatus according to claim 17, wherein the network interface circuit includes an asynchronous transfer mode transmission convergence (ATM TC) circuit on said single chip.

19. The single chip network adapter apparatus according to claim 18, wherein the network interface circuit includes an asynchronous transfer mode segmentation and reassembly (ATM SAR) circuit on said single chip.

8. A host system connected to a network, comprising in combination:

a host processor;

a host system bus coupled to the host processor for transferring digital data to and from the host processor;

host random access memory coupled to the host system bus for storing digital data; and

a network adapter apparatus constructed on a single semiconductor substrate having a first port coupled to the host system bus and having a second port coupled to a network, the apparatus including a host bus interface circuit coupled to the first port, a direct memory access controller circuit coupled to the host bus interface circuit for transferring digital data to and from the host random access memory, a microprocessing unit coupled to the host bus interface circuit, random access memory RAM for storing information in a network protocol format and in a host computer format, said RAM coupled to the microprocessing unit, a network interface circuit coupled to the second port and coupled to the microprocessing unit, the microprocessing unit being operative to format digital data received from the host system bus into packets of data consistent with a network protocol and to format digital data received via the second port into packets of data consistent with a network protocol suitable for the host system bus.

9. The host system according to claim 8, wherein the processing unit comprises a reduced instruction set computer (RISC)-based processor.

10. The host system according to claim 8, wherein the processing unit comprises a logic controller circuit.

11. The host system according to claim 8, wherein the network is an asynchronous transfer mode (ATM) network.

12. The host system according to claim 8, wherein the network is an Ethernet network.

13. The host system according to claim 8, wherein the network is a fiber distributed data interface (FDDI) network.

14. The host system according to claim 8, wherein the host system bus is a parallel cell interface (PCI) bus.

15. The host system according to claim 8, wherein the host system bus is an extended industry standard architecture (EISA) bus.

16. The host system according to claim 8, wherein the host system bus is an S-bus.

20. A single chip network adapter apparatus on a single semiconductor substrate, comprising:

a PMD circuit for interconnection to an ATM network;

a TC/Framer circuit coupled to the PMD circuit;

an ATM SAR circuit coupled to the PMD circuit;

microprocessor means coupled to the ATM SAR circuit for converting ATM packets of data to an internal data format;

an internal data bus coupled to said microprocessor means for converting ATM packets of data;

a direct memory access controller coupled to the internal data bus; and

a PCI bus interface circuit coupled to the direct memory access controller, and being adapted for connection to an external data bus, whereby data in the internal data format can be transferred to and from an external bus;

each of the components of the single chip network adapter apparatus being disposed on a single semiconductor substrate.

21. The single chip network adapter apparatus according to claim 20, further comprising random access memory on said single substrate for temporarily storing packets of digital information in an ATM network protocol format, the random access memory being coupled to said means for converting ATM packets of data.

22. A single chip network adapter apparatus on a single semiconductor substrate, comprising;

a physical layer circuit for interfacing to an ATM network;

an ATM cell interface circuit coupled to the physical layer circuit;

a virtual channel RAM (VCR) coupled to the ATM cell interface;

a DMA-VCR bus coupled to the virtual channel RAM;

a direct memory access controller coupled to the DMA-VCR bus;

a random access memory for storing packets of data in an ATM network protocol format, the random access memory being coupled to the direct memory access controller;

an internal data bus coupled to the direct memory access controller;

an ATM microprocessing unit (APU) for converting data in an ATM network protocol format to an internal data format, said APU being coupled to the internal data bus;

a host data bus coupled to the direct memory access controller;

a shared host RAM memory coupled to the host data bus for storing data in the internal data format; and

a host processor coupled to the host data bus;

each of the components of the single chip network adapter apparatus being disposed on a single semiconductor substrate.

23. The single chip network adapter apparatus according to claim 22, further comprising on said single semiconductor substrate:

a pacing rate unit coupled to the internal data bus and coupled to the APU.

24. The single chip network adapter apparatus according to claim 23, further comprising on said single semiconductor substrate:

an instruction RAM coupled to the APU for storing instructions to be executed by the APU.

25. A single chip network adapter apparatus on a single semiconductor substrate, comprising:

means for interconnecting to an ATM network;

a random access memory for storing ATM cells;

means for processing and segmentation and reassembly, said means being coupled to the means for interconnecting to an ATM network;

a microprocessor for converting ATM cells to an internal data format, said microprocessor being coupled to the means for storing ATM cells;

an internal data bus coupled to said means for converting ATM packets of data;

a direct memory access means coupled to the internal data bus for controlling transfers of information to and from said random access memory; and

external bus interface means for connection to an external data bus, said means being coupled to the direct memory access means;

each of the components of the single chip network adapter apparatus being disposed on a single semiconductor substrate.