Microcontroller system for performing operations of multiple microcontrollers

• US 5,887,189 A
• Filed: 01/21/1997
• Issued: 03/23/1999
• Est. Priority Date: 09/19/1994
• Status: Expired due to Fees

• Current Assignee: Adelante Technologies B.V.
• Original Assignee: Philips Electronics North America Corporation (Koninklijke Philips N.V.)
• Inventors: Birns, Neil E., Mizrahi-Shalom, Ori K.
• Primary Examiner(s): Donaghue, Larry D.
• Assistant Examiner(s): Nguyen, Dzung C.
• Application Number:
  US08/786,513
• Time in Patent Office: 791 Days
• Field of Search: 395/800, 395/800.01, 395/401, 395/427, 395/412, 395/413, 395/421.01, 395/421.07, 395/421.09, 395/421.1, 395/800.32, 395/800.36, 364/DIG. 1, 711/262, 711/203, 711/206, 711/209, 711/212
• US Class Current: 712/32
• CPC Class Codes: G06F 9/462 with multiple register sets
• CPC Class Codes: G06F 9/5016 the resource being the memory

Abstract

A microcontroller that provides an environment to run processes developed to run on several prior or low end generation machines with the independent register, status and data space needed for execution, that is, the resources of the microcontroller are a superset of the resources of the prior generation machine. The ability to limit one process from accessing the data space of another independent process is provided by data space segmentation controlled by upper order address bits not accessible by the independent processes. The separate workspaces are configured substantially like a workspace of a prior or low end generation machine allowing the microcontroller to perform the tasks of several independent prior or low end generation machines working in concert.

Claims

1. An electronic circuit with a microcontroller having an operational mode for running multiple application programs, the circuit comprising:

a register file with a plurality of banks of registers;

a data memory;

address mapping logic;

wherein in the operational mode;

the address mapping logic is operative to truncate a memory address used in a respective one of the programs and to map the truncated address on a respective bank of registers dependent on the truncated address falling in a particular range

wherein;

the plurality of banks of registers comprises first banks of general purpose registers and second banks of special function registers;

the address mapping logic is operative to;

truncate the address by ignoring a number of its most significant bits;

mapping a first range of truncated addresses of the data memory used by the respective program into respective ones of the first banks of general purpose registers; and

mapping a second range of truncated addresses into respective ones of the second banks of special function registers when direct addressing is employed.

2. The circuit of claim 1, wherein:

the first range is smaller than 1F hex; and

the second range lies between 400 hex and 7FF hex.

3. The circuit of claim 2, wherein any of the multiple application programs is a program that is code compatible with a further program for a 80C51-type controller.