Enhanced DRAM with embedded registers
First Claim
1. An integrated circuit memory device comprising:
- a memory array;
a cache integrated within and coupled for direct mapping by row address to said memory array;
a column address latch coupled to said memory array;
an address input coupled to said column address latch;
a last row read address latch coupled to said cache and said address input;
a comparator coupled to said last read row address latch and said address input;
a row address latch coupled to said memory array and said address input;
a refresh counter coupled to said memory array;
an input and output control circuit coupled to said memory array and said cache;
an output coupled to said input and output control circuit; and
a plurality of input/output data lines and masking circuitry so that said plurality of input/output data lines are maskable.
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Accused Products
Abstract
An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data. This data corresponds to data stored in the DRAM at a particular address. When an address is supplied to the DRAM, it is compared to the address of the data stored in the cache. If the addresses are the same, then the cache data is read at SRAM speeds. The DRAM is decoupled from this read. The DRAM also remains idle during this cache read unless the system opts to precharge or refresh the DRAM. Refresh or precharge occur concurrently with the cache read. If the addresses are not the same, then the DRAM is accessed and the embedded register is reloaded with the data at that new DRAM address. Asynchronous operation of the DRAM is achieved by decoupling the row registers from the DRAM array, thus allowing the DRAM cells to be precharged or refreshed during a read of the row register.
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Citations
32 Claims
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1. An integrated circuit memory device comprising:
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a memory array; a cache integrated within and coupled for direct mapping by row address to said memory array; a column address latch coupled to said memory array; an address input coupled to said column address latch; a last row read address latch coupled to said cache and said address input; a comparator coupled to said last read row address latch and said address input; a row address latch coupled to said memory array and said address input; a refresh counter coupled to said memory array; an input and output control circuit coupled to said memory array and said cache; an output coupled to said input and output control circuit; and a plurality of input/output data lines and masking circuitry so that said plurality of input/output data lines are maskable.
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2. An integrated circuit memory comprising:
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a plurality of connection pins; an integrated circuit connected to said connection pins, the integrated circuit including a plurality of DRAM memory cells arranged in an array, a plurality of row registers coupled selectively to said array, a coupling circuit connected between said array and said row registers and effective for selectively coupling and decoupling the array from the row registers, a row decoder coupled to said array, a refresh circuit coupled to said array, a precharging circuit coupled to said coupling circuitry for allowing said array to be precharged while at least one of said plurality of row registers is accessed, a column decoder, a plurality of sense amplifiers coupled to said array, and at least one output data buffer; wherein said plurality of pins includes; a plurality of address pins for receiving row and column addresses; a plurality of power supply pins for receiving power supply voltages; a plurality of data pins for receiving and outputting data bits; a chip select pin for receiving a chip select signal; a write enable pin for receiving a write enable signal; a row enable pin for receiving a row enable signal; and a column address latch pin for receiving a column address latch signal. - View Dependent Claims (3, 4, 5)
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6. A method of operating an integrated circuit memory having a DRAM portion, an on-chip cache portion coupled to the DRAM portion, and a plurality of connection pins, comprising the steps of:
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applying row and column addresses to a plurality of address pins; applying input data to a plurality of data pins in connection with a storing step where the input data is to be stored in the DRAM portion; receiving all output data only from the on-chip cache portion of the integrated circuit memory via said plurality of data pins; applying a chip select signal to a chip select pin for enabling the on-chip cache portion to be activated so that data can be read therefrom without requiring access to the DRAM portion; and applying a row enable signal to a row enable pin to permit the DRAM portion to be accessed for writing to or reading from the DRAM portion. - View Dependent Claims (7, 8, 9, 10)
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11. A method of operating an integrated circuit memory having a DRAM portion, an on-chip cache portion coupled to the DRAM portion, and a plurality of connection pins, comprising the steps of:
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(a) reading from the on-chip cache portion including the sub-steps of; applying row and column addresses to a plurality of address pins, applying input data to a plurality of data pins in connection with a storing step where the input data is to be stored in the DRAM portion, receiving output data from said data pins representing data stored in the integrated circuit memory, applying a column address latch signal to a column address latch pin to control a column address latch in the integrated circuit memory, applying a chip select signal to a chip select pin for enabling the onchip cache portion to be activated so that data can be read therefrom without requiring access to the DRAM portion, and applying a row enable signal to a row enable pin to permit the DRAM portion to be accessed for writing to or reading from the DRAM portion; and (b) precharging the DRAM portion, wherein steps (a) and (b) are performed contemporaneously. - View Dependent Claims (12, 13, 14, 15, 16)
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17. A method for data storage access in a memory chip including an integrated circuit cache memory and an integrated circuit memory array, the method comprising the steps of:
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reading from the integrated circuit cache memory; decoupling the integrated circuit memory array from the integrated circuit cache memory simultaneously with said reading step; and asynchronously precharging the integrated circuit memory array contemporaneously with said reading step. - View Dependent Claims (18)
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19. A method for data storage access comprising the step of:
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inputting a row address to a single chip memory device; on said single chip, comparing said row address to a last read row address; if said row address and said last read row address are equal, terminating internally a main selection input signal, reading from a cache located on said single chip memory device, and outputting from said cache without reading from a memory array portion of the single chip memory device. - View Dependent Claims (20, 21, 22)
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23. An integrated circuit memory device comprising:
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a memory array; a cache integrated within and coupled for mapping by row address to said memory array; a column address latch coupled to said memory array; an address input coupled to said column address latch; a row address latch coupled to said memory array and said address input; an input and output control circuit coupled to said memory array and said cache; an output coupled to said input and output control circuit; and a plurality of input/output data lines, and masking circuitry so that said plurality of input/output data lines are maskable. - View Dependent Claims (24, 25, 26)
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27. A method for operating an integrated circuit memory device including a dynamic random access memory array having a single row decoder, a single column decoder responsive to an externally supplied address signal on an address bus for accessing a specified subset of memory cells within said memory array, a bidirectional data bus for providing a signal indicative of data associated with the specified subset of memory cells, an input/output control and data latch circuit responsive to an externally applied write enable signal and being coupled to input and output buses of the bidirectional data bus, a memory cache for storing a row of the data associated with the specified subset of memory cells last accessed from the memory device and coupled to the input and output buses and to an associated column write select circuit and interposed between the single column decoder and the memory array, wherein corresponding locations in rows of both the memory cache and the memory array may be accessed by the single column decoder, and wherein data read from the memory device is read out of the memory cache only and data written to the memory device is written to the memory array, the method comprising the steps of:
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reading from the memory cache; decoupling the memory array from the memory cache simultaneously with said reading step; and asynchronously operating the memory array contemporaneously with said reading step. - View Dependent Claims (28, 29)
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30. A memory chip comprising:
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an integrated circuit cache memory; an integrated circuit memory array; an output circuit for outputting data from the integrated circuit cache memory; a decoupling circuit for decoupling the integrated circuit memory array from the integrated circuit cache memory when data is being output from the output circuit; and a precharging circuit coupled to the decoupling circuit for precharging the integrated circuit memory array contemporaneously with the output circuit outputting data from the integrated circuit cache memory. - View Dependent Claims (31)
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32. A memory chip comprising:
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a cache; a memory array coupled to the cache and for outputting data based on a main selection input signal; row address pins for receiving a row address applied to the memory chip; a comparator for comparing the row address to a last read row address and outputting a positive result if the row address and the last read row address are equal; an internal cache controller responsive to the positive result of the comparator, the internal cache controller including (a) a terminator for unasserting a main selection input signal and (b) an output circuit for outputting data from the cache without reading from the memory array.
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Specification