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Enhanced DRAM with embedded registers

  • US 5,887,272 A
  • Filed: 07/03/1997
  • Issued: 03/23/1999
  • Est. Priority Date: 01/22/1992
  • Status: Expired due to Term
First Claim
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1. An integrated circuit memory device comprising:

  • a memory array;

    a cache integrated within and coupled for direct mapping by row address to said memory array;

    a column address latch coupled to said memory array;

    an address input coupled to said column address latch;

    a last row read address latch coupled to said cache and said address input;

    a comparator coupled to said last read row address latch and said address input;

    a row address latch coupled to said memory array and said address input;

    a refresh counter coupled to said memory array;

    an input and output control circuit coupled to said memory array and said cache;

    an output coupled to said input and output control circuit; and

    a plurality of input/output data lines and masking circuitry so that said plurality of input/output data lines are maskable.

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