Method of dividing a wafer and method of manufacturing a semiconductor device

• US 5,888,883 A
• Filed: 04/24/1998
• Issued: 03/30/1999
• Est. Priority Date: 07/23/1997
• Status: Expired due to Term

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Takyu, Shinya, Sasaki, Shigeo, Tokubuchi, Keisuke, Yazima, Koichi
• Primary Examiner(s): Picardat, Kevin M.
• Application Number:
  US09/065,626
• Time in Patent Office: 340 Days
• Field of Search: 438/460, 438/461, 438/462, 438/463, 438/464, 438/465, 438/977
• US Class Current: 438/460
• CPC Class Codes: H01L 21/3043 Making grooves, e.g. cutting
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4826 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/0132 Binary Alloys
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

Grooves are formed in a surface of a wafer, on which surface semiconductor elements are formed, along dicing lines. The grooves are deeper than a thickness of a finished chip. A holding member is attached on the surface of the wafer on which the semiconductor elements are formed. A bottom surface of the wafer is lapped and polished to the thickness of the finished chip, thereby dividing the wafer into chips. When the wafer is divided into the chips, the lapping and polishing is continued until the thickness of the wafer becomes equal to the thickness of the finished chip, even after the wafer has been divided into the chips by the lapping and polishing.

Claims

1. A wafer dividing method comprising the steps of:

forming grooves in a surface of a wafer, on which surface semiconductor elements are formed, along dicing lines, said grooves being deeper than a thickness of a finished chip;

attaching a holding member on said surface of the wafer on which the semiconductor elements are formed; and

lapping and polishing a bottom surface of the wafer to said thickness of the finished chip, thereby dividing the wafer into chips,

wherein in the step of dividing the wafer into the chips, the lapping and polishing is continued until the thickness of the wafer becomes equal to the thickness of the finished chip, even after the wafer has been divided into the chips by the lapping and polishing.

2. The wafer dividing method according to claim 1, wherein a depth of each groove is greater than the thickness of the finished chip by at least 5 μ

m.

3. The wafer dividing method according to claim 1, wherein said holding member is at least one selected from the group consisting of an adhesive tape, a wax, an adsorption pad, a thermocompression bonding sheet, a substrate coated with adhesive material, and a resist coated on a semiconductor element.

4. A method of manufacturing a semiconductor device, comprising the steps of:

forming a semiconductor elements in a major surface of a wafer;

forming grooves in said major surface of the wafer along dicing lines, said grooves being deeper than a thickness of a finished chip;

attaching an adhesive sheet on said major surface of the wafer;

lapping and polishing a bottom surface of the wafer to said thickness of the finished chip, thereby dividing the wafer into chips; and

separating each of the divided chips from the adhesive sheet and sealing said each chip in a package,

wherein in the step of dividing the wafer into the chips, the lapping and polishing is continued until the thickness of the wafer becomes equal to the thickness of the finished chip, even after the wafer has been divided into the chips by the lapping and polishing.

5. The method of manufacturing a semiconductor device, according to claim 4, wherein a depth of each groove is greater than the thickness of the finished chip by at least 5 μ

m.

6. The method of manufacturing a semiconductor device, according to claim 4, wherein said step of separating each of the divided chips from the adhesive sheet and sealing said each chip in the package comprises the steps of:

mounting said each chip separated from the adhesive sheet on an island of a lead frame;

wire-bonding inner lead portions of the lead frame and pads of said chip; and

sealing said chip, said island and said inner lead portions in the package.

7. The method of manufacturing a semiconductor device, according to claim 4, wherein said step of separating each of the divided chips from the adhesive sheet and sealing said each chip in the package comprises the steps of:

bonding one end of a lead on major surface of the chip separated from the adhesive sheet;

wire-bonding said lead and each of pads of said chip; and

sealing said chip and said one end of the lead in the package.

8. The method of manufacturing a semiconductor device, according to claim 7, wherein said step of separating each of the divided chips from the adhesive sheet and sealing said each chip in the package further comprises a step of bonding said one end of the lead to the major surface of the chip, with an adhesive tape interposed between the major surface of the chip and the lead, a thickness of said adhesive tape being greater than a thickness of silicon waste produced in the step of lapping and polishing the bottom surface of the wafer.