Electronic device pad relocation, precision placement, and packaging in arrays
First Claim
1. A method for making an array of closely-spaced devices, said method comprising:
- providing a semiconductor wafer having front and rear major surfaces, the wafer including a plurality of active device regions separated by scribe lanes, with top interconnection pads on the front major surface;
forming holes through the wafer within the scribe lanes;
forming an electrically insulating layer on all exposed surfaces of the wafer, including within the holes, with openings in the insulating layer for access to the top interconnection pads;
metallizing and patterning the wafer and the holes to form bottom interconnection pads and alignment pads on the rear major surface, the bottom interconnection pads electrically connected to corresponding interconnection pads by metallization extending within the holes;
employing a dicing saw having a kerf width less than the diameter of the holes to saw within at least some of the scribe lanes to separate the wafer into segments each including at least one device active region;
providing a substrate having at least two electrical connection pads positioned for mating with the alignment pads;
forming a rigid alignment structure on the substrate and projecting from the substrate for mechanical engagement with the devices; and
placing the devices on the substrate and attaching the alignment pads to the electrical connection pads, whereby the rigid alignment structure provides accurate position alignment.
1 Assignment
0 Petitions
Accused Products
Abstract
Top die pads are electrically relocated by forming holes through a semiconductor wafer between device active regions. An electrically insulating layer is formed over all exposed surfaces of the wafer, including within the holes, and openings are made in the insulating layer for access to the top interconnection pads. The wafer and holes are metallized and patterned to form bottom interconnection pads electrically connected to corresponding top interconnection pads by metallization extending within the holes. A dicing saw having a kerf width less than the diameter of the holes is employed to separate the individual devices. For accurate position alignment of repatterned die, an alignment structure, such as projecting pins or an egg crate structure, engages the die, and alignment pads can be patterned on the die.
299 Citations
20 Claims
-
1. A method for making an array of closely-spaced devices, said method comprising:
-
providing a semiconductor wafer having front and rear major surfaces, the wafer including a plurality of active device regions separated by scribe lanes, with top interconnection pads on the front major surface; forming holes through the wafer within the scribe lanes; forming an electrically insulating layer on all exposed surfaces of the wafer, including within the holes, with openings in the insulating layer for access to the top interconnection pads; metallizing and patterning the wafer and the holes to form bottom interconnection pads and alignment pads on the rear major surface, the bottom interconnection pads electrically connected to corresponding interconnection pads by metallization extending within the holes; employing a dicing saw having a kerf width less than the diameter of the holes to saw within at least some of the scribe lanes to separate the wafer into segments each including at least one device active region; providing a substrate having at least two electrical connection pads positioned for mating with the alignment pads; forming a rigid alignment structure on the substrate and projecting from the substrate for mechanical engagement with the devices; and placing the devices on the substrate and attaching the alignment pads to the electrical connection pads, whereby the rigid alignment structure provides accurate position alignment. - View Dependent Claims (2, 3, 4, 5)
-
-
6. A method for making an array of closely-spaced imaging or display devices, comprising:
-
providing a semiconductor wafer having front and rear major surfaces, the wafer including a plurality of active device regions on the front major surface separated by scribe lanes, with top interconnection pads on the front major surface; forming holes through the wafer within the scribe lanes; forming an electrically insulating layer on all exposed surfaces of the wafer, including within the holes, with openings in the insulating layer for access to the top interconnection pads; metallizing and patterning the wafer and the holes to form bottom interconnection pads on the rear major surface electrically connected to corresponding to interconnection pads by metallization extending within the holes; sawing within at least some of the scribe lanes to separate the wafer into segments each including at least one device active region; placing and attaching the segments front major surface down on an optically transparent substrate; forming a multilayer interconnect structure overlying the rear major surfaces of the wafer segments in electrical connection with the bottom interconnection pads. - View Dependent Claims (7, 8, 9, 11)
-
-
10. A method for making an array of closely-spaced devices, comprising:
-
Providing a semiconductor wafer having front and rear major surfaces, the wafer including a plurality of active device regions on the front major surface separated by scribe lanes, with top interconnection Dads on the front major surface; forming holes through the wafer within the scribe lanes; forming an electrically insulating layer on all exposed surfaces of the wafer, including within the holes, with openings in the insulating layer for access to the top interconnection pads; metallizing and patterning the wafer and the holes to form bottom interconnection pads on the rear major surface electrically connected to corresponding to interconnection pads by metallization extending within the holes; sawing within at least some of the scribe lanes to separate the wafer into segments each including at least one device active region; placing and attaching the segments front major surface down on a substrate comprising a stretched polymer film; forming a multilayer interconnect structure overlaying the rear major surfaces of the wafer segments in electrical connection with the bottom interconnection pads employing a curved tool to establish an array curvature.
-
-
12. A method for making a multi-device electronic package including a plurality of devices having major surfaces, with interconnection pads on one of the major surfaces, said method comprising:
-
providing a substrate and forming a rigid alignment structure on the substrate and projecting from the substrate for mechanical engagement with the devices; placing and attaching the devices to the substrate with the interconnection pads facing up, whereby the rigid alignment structure provides accurate position alignment; and forming a multilayer interconnect structure overlying the devices and interconnecting selected ones of the interconnection pads. - View Dependent Claims (13)
-
-
14. A method for fixing an array of electrical devices having front and rear major surfaces in precise locations on a support substrate, said method comprising the steps of:
-
forming a rigid alignment structure on the substrate and projecting from the substrate for mechanical engagement with the devices; and placing and attaching the devices to the substrate, whereby the rigid alignment structure provides accurate position alignment. - View Dependent Claims (15, 16, 17, 18, 19, 20)
-
Specification