Metal layer pattern forming method

• US 5,888,892 A
• Filed: 05/22/1996
• Issued: 03/30/1999
• Est. Priority Date: 05/24/1995
• Status: Expired due to Term

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Yanagida, Toshiharu
• Primary Examiner(s): Everhart, Caridad
• Application Number:
  US08/650,271
• Time in Patent Office: 1,042 Days
• Field of Search: 438/612, 438/613, 438/614, 438/576, 438/577, 438/578, 438/951
• US Class Current: 438/614
• CPC Class Codes: H01L 21/0272 for lift-off processes
• CPC Class Codes: H01L 21/7688 by deposition over sacrificial masking layer, e.g. lift-off lift-off per se H01L21/0272
• CPC Class Codes: H01L 2224/0347 using a lift-off mask
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05073 Single internal layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/11472 Profile of the lift-off mask
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01018 Argon [Ar]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01024 Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01061 : Promethium [Pm]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: Y10S 438/951 : Lift-off

Abstract

Disclosed is a metal layer pattern forming method which easily allows lift-off. The thickness of the photoresist layer is not less than double the thickness of the metal layer, and the maximum temperature that the surface of the substrate to be processed attains ranges from 100° C. to 150° C. Through appropriate improvement of the quality of the photoresist layer, bonding to the background is prevented and the lift-off is facilitated.

Claims

1. A semiconductor device manufacturing method comprising the steps of:

forming an electrode pad on a semiconductor base;

forming a passivation layer having an opening on said electrode pad and further forming a photoresist layer having an opening on the passivation layer such that at least a part of said electrode pad is exposed through the opening of said passivation layer and the opening in said photoresist layer;

deforming said photoresist while cooling the semiconductor base;

forming a metal layer on said photoresist and on the exposed portion of said electrode pad; and

removing said photoresist.

2. A semiconductor device manufacturing method according to claim 1, wherein the step of deforming said photoresist is effected by a plasma processing.

3. A method for making a semiconductor device, comprising the steps of:

forming an electrode pad on a semiconductor base;

forming a passivation layer on said electrode pad and semiconductor base including an opening therein having a first width and exposing a portion of the electrode pad;

forming a photoresist layer having a thickness on the passivation layer, said photoresist layer including an opening therein having a second larger width and exposing a portion of the passivation layer and the exposed portion of the electrode pad, the photoresist layer including an upstanding edge portion disposed about said opening;

plasma processing the photoresist layer with a plasma having a plasma density of from greater than or equal to about 1×

10¹¹ particles/cm³ to less than about 1×

10¹⁴ particles/cm³ to provide a deformed photoresist layer including an undercut and an overhanging portion defined in the upstanding edge portion;

forming a metal layer having a thickness on the deformed photoresist and exposed portions of the passivation layer and electrode pad; and

thereafter, removing said photoresist, wherein the thickness of the photoresist layer is not less than double the thickness of the metal layer.

4. A semiconductor device manufacturing method according to claim 3, wherein said metal layer has a layered structure comprising a chrome layer, a copper layer and a gold layer.

5. A semiconductor device manufacturing method according to claim 3, wherein the step of removing said photoresist is performed by wet etching.

6. A semiconductor device manufacturing method according to claim 3, wherein the thickness of said photoresist is not less than 3 μ

m.

7. A method for making a semiconductor device, comprising the steps of:

forming an electrode pad on a semiconductor base;

forming a passivation layer on said electrode pad and semiconductor base including an opening therein having a first width and exposing a portion of the electrode pad;

forming a photoresist layer having a thickness on the passivation layer, said photoresist layer including an opening therein having a second larger width and exposing a portion of the passivation layer and the exposed portion of the electrode pad, the photoresist layer including an upstanding edge portion disposed about said opening;

plasma processing the photoresist layer with a plasma in an inert gas atmosphere to provide a deformed photoresist layer including an undercut and an overhanging portion defined in the upstanding edge portion;

forming a metal layer having a thickness on the deformed photoresist and exposed portions of the passivation layer and electrode pad; and

thereafter, removing said photoresist, wherein the thickness of the photoresist layer is not less than double the thickness of the metal layer.

8. A semiconductor device manufacturing method according to claim 7, wherein said metal layer has a layered structure comprising a chrome layer, a copper layer and a gold layer.

9. A semiconductor device manufacturing method according to claim 7, wherein the step of removing said photoresist is performed by wet etching.

10. A semiconductor device manufacturing method according to claim 7, wherein the thickness of said photoresist is not less than 3 μ

m.

11. A semiconductor device manufacturing method according to claim 7, wherein in the plasma processing step the inert gas atmosphere comprises argon gas.