Vertical JFET field effect transistor

• US 5,889,298 A
• Filed: 04/30/1993
• Issued: 03/30/1999
• Est. Priority Date: 04/30/1993
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Yuan, Han-Tzong, Plumton, Donald Lynn
• Primary Examiner(s): GUAY, JOHN FRANCIS
• Application Number:
  US08/056,681
• Time in Patent Office: 2,160 Days
• Field of Search: 257/287, 257/279, 257/285, 257/263, 257/266
• US Class Current: 257/285
• CPC Class Codes: H01L 21/02395 Arsenides
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/02463 Arsenides
• CPC Class Codes: H01L 21/02546 Arsenides
• CPC Class Codes: H01L 21/02576 N-type
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 29/66318 Heterojunction transistors
• CPC Class Codes: H01L 29/66924 with an active layer made of a group 13/15 material H01L29/66446 takes precedence
• CPC Class Codes: H01L 29/7371 Vertical transistors
• CPC Class Codes: H01L 29/7722 using static field induced regions, e.g. SIT, PBT

Abstract

A vertical field effect transistor (700) and fabrication method with buried gates (704) having gate sidewall crystal orientation the same as the substrate surface and a low index substrate crystal orientation without tilt to a higher index direction. The gate (704) may have modulated doping along the channel (706), and the drain (708) may have a lighter doping level than the channel which may be accomplished by an epitaxial overgrowth of the gates (704) to form the channels (706).

Claims

1. A field effect transistor, comprising:

(a) a source region in a semiconductor layer;

(b) a drain region in said semiconductor layer;

(c) a gate region in said semiconductor layer and between said source region and said drain region;

(d) a channel region in said semiconductor layer and between said source region and said drain region and abutting said gate region;

(d) wherein said gate region has a doping level where said gate region abuts said channel region varying in the direction from said source region to said drain region.

2. The transistor of claim 1, wherein:

(a) said gate region includes a first subregion abutting said drain and a second subregion away from said drain, wherein said first subregion has a doping level less than the doping level of said second subregion.

3. The transistor of claim 2, wherein:

(a) said layer is made of gallium arsenide;

(b) said gate region is doped p-type with carbon; and

(c) said source, drain, and channel regions are doped n-type with silicon.

4. The transistor of claim 1, wherein:

(a) carrier flow from said source region, through said channel region, and into said drain region is substantially perpendicular to a surface of said semiconductor layer.

5. The transistor of claim 4, wherein:

(a) said gate region includes a plurality of parallel fingers with portions of said channel region between successive ones of said parallel fingers.

6. The transistor of claim 5, wherein:

(a) said layer is made of gallium arsenide;

(b) said gate region is doped p-type with carbon; and

(c) said source, drain, and channel regions are doped n-type with silicon.

7. The transistor of claim 1, wherein:

(a) said gate region includes successive subregions S₁, S₂, . . . S_K in the direction from said drain to said source with K a positive integer greater than 2, wherein the doping level of S₂ differs from that of S₁ and the doping level of S_K-1 differs from than that of S_K.

8. The transistor of claim 7, wherein:

(a) K equals 3; and

(b) the doping levels of S₁ and S₃ are equal and less than that of S₂.

9. The transistor of claim 7, wherein:

(a) S₁ and S₃ are doped more heavily than S₂.

10. The transistor of claim 7, wherein:

(a) K equals 5; and

(b) the doping levels of S₁, S₃, and S₅ are less than those of S₂ and S₄.

11. The transistor of claim 7, wherein:

(a) said layer is made of gallium arsenide;

(b) said gate region is doped p-type with carbon; and

(c) said source region, drain region, and channel region are doped with silicon.

12. The transistor of claim 7, wherein:

(a) carrier flow from said source region, through said channel region, and into said drain region is substantially perpendicular to a surface of said semiconductor layer.

13. The transistor of claim 12, wherein:

(a) said gate region includes a plurality of parallel fingers with portions of said channel region between successive ones of said parallel fingers.

14. The transistor of claim 7, wherein:

(a) the doping type of S_j, for a j greater than 1 and less than K, is opposite the doping type of S₁ and S_K, whereby said gate is split into two subgates.

15. The transistor of claim 7, wherein:

(a) S₁ is made of a first semiconductor material and S_K is made of a second semiconductor material with a said first material having a larger bandgap than said second material.