Electrostatic discharge protection circuit

• US 5,889,309 A
• Filed: 12/19/1996
• Issued: 03/30/1999
• Est. Priority Date: 11/07/1996
• Status: Expired due to Term

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: Winbond Electronics Corporation
• Inventors: Yu, Ta-Lee, Wu, Chau-Neng, Yeh, Ling-Yen, S-T Lin, Frank, Young, Konrad
• Primary Examiner(s): CRANE, SARA W
• Application Number:
  US08/770,650
• Time in Patent Office: 831 Days
• Field of Search: 257/362, 257/361, 257/355, 257/356, 257/357, 257/358, 257/360, 257/363, 257/555, 257/556, 257/575, 257/173
• US Class Current: 257/363
• CPC Class Codes: H01L 27/0259 using bipolar transistors as protective elements
• CPC Class Codes: H01L 27/0658 Vertical bipolar transistor in combination with resistors or capacitors

Abstract

An electrostatic discharge protection circuit formed in a semiconductor substrate includes a vertical bipolar junction transistor having a base which is grounded, an emitter connected to an output/input bonding pad of an integrated circuit, and a collector connected to a high power source via a resistor. The resistor is a parasitic resistor created by controlling the distance between the diffusion regions or the distance between a p-type well region and an n-type well region or formed by a lightly doped diffusion region in the semiconductor substrate to prevent current crowding and increase electrostatic protection.

Claims

1. An electrostatic discharge protection circuit which during operation is connected to first and second power nodes, said protection circuit formed in a semiconductor substrate, comprising:

a single p-type well inside said semiconductor substrate;

a first diffusion region of n-type located in said p-type well to provide a signal input end;

a second diffusion region of p-type located in said p-type well and connected to the first power node;

an n-type well contacting said p-type well in said semiconductor substrate;

a third diffusion region of n-type connected to the second power node and located in said n-type well; and

a fourth diffusion region being more lightly doped than said n-type well and located within said n-type well and located between said p-type well and said third diffusion region.

2. The electrostatic discharge protection circuit as claimed in claim 1 wherein said fourth diffusion region is an n^- -type diffusion region.

3. The electrostatic discharge protection circuit as claimed in claim 1, further comprising an output/input bonding pad of an integrated circuit and wherein said signal input end is connected to said output/input bonding pad of an integrated circuit.

4. An electrostatic discharge protection circuit which during operation is connected to first and second power nodes, said protection circuit formed in a semiconductor substrate of a first conductivity type, said protection circuit comprising:

a single well of a second conductivity type formed inside said semiconductor substrate;

a first diffusion region of the first conductivity type located in said well that provides a signal input end;

a second diffusion region of the second conductivity type located in said well and connected to the first power node; and

a third diffusion region of the first conductivity type connected to the second power node and located in said semiconductor substrate, said third diffusion region spaced from said well by a distance of about 3 to 10 microns.

6. The electrostatic discharge protection circuit of claim 4, further comprising an integrated circuit pad located on said substrate and wherein said signal input end is connected to the integrated circuit pad.

7. The electrostatic discharge protection circuit of claim 6, further comprising a fourth diffusion region of the second conductivity type located in said semiconductor substrate and connected to the integrated circuit pad.

10. The electrostatic discharge protection circuit of claim 4, wherein the first and second conductivity types are p-type and n-type, respectively.

11. The electrostatic discharge protection circuit of claim 4, wherein the first and second conductivity types are n-type and p-type, respectively.

5. An electrostatic discharge protection circuit which during operation is connected to first and second power nodes, said protection circuit formed in a semiconductor substrate of n-type, comprising:

a single p-type well inside said semiconductor substrate;

a first diffusion region of p-type located in said p-type well to provide a signal input end;

a second diffusion region of n-type located in said p-type well and connected to the first power node;

an n-type well near said p-type well in said semiconductor substrate; and

a third diffusion region connected to the second power node, located in said n-type well and maintained at a distance of about 3-10 microns from said p-type well.

8. The electrostatic discharge protection circuit of claim 5, further comprising an integrated circuit pad located on said substrate and wherein said signal input end is connected to the integrated circuit pad.

9. The electrostatic discharge protection circuit of claim 8, further comprising a fourth diffusion region located in said semiconductor substrate and connected to the integrated circuit pad.