Semiconductor structure having two levels of buried regions

• US 5,889,315 A
• Filed: 02/23/1995
• Issued: 03/30/1999
• Est. Priority Date: 08/18/1994
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Merrill, Richard B., Saha, Samar, Brehmer, Kevin E., Gadepally, Kamesh, Cacharelis, Philip J., Farrenkopf, Douglas R.
• Primary Examiner(s): Prenty, Mark V.
• Application Number:
  US08/393,622
• Time in Patent Office: 1,496 Days
• Field of Search: 257/552, 257/565, 257/593, 257/655, 257/657, 257/370, 257/378, 257/544, 257/545, 257/549
• US Class Current: 257/552
• CPC Class Codes: H01L 21/761 PN junctions
• CPC Class Codes: H01L 21/822 the substrate being a semiconductor, using silicon technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/8249 Bipolar and MOS technology
• CPC Class Codes: H01L 27/0203 Particular design considerations for integrated circuits
• CPC Class Codes: H01L 27/0623 in combination with bipolar transistors
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: Y10S 148/085 Isolated-integrated

Abstract

Integrated circuits suitable for high-performance applications, especially mixed signal products that have analog and digital sections, are fabricatable from a semiconductor structure having two levels of buried regions. In a typical embodiment lower buried regions of opposite conductivity types are situated along a lower semiconductor interface between a semiconductive substrate and an overlying lower semiconductive layer. Upper buried regions of opposite conductivity type are similarly situated along an upper semiconductor interface between the lower semiconductive layer and an overlying upper semiconductive layer. The upper semiconductive layer contains P-type and N-type device regions in which transistor zones are situated. The semiconductor structure is normally configured so that at least one of each of the P-type and N-type device regions is electrically isolated from the substrate. Complementary bipolar transistors can be integrated with complementary field-effect transistors in the structure.

Claims

1. A semiconductor structure comprising (a) a monocrystalline semiconductive substrate, (b) a lower monocrystalline semiconductive layer that overlies the substrate and adjoins it along a lower semiconductor interface, and (c) an upper monocrystalline semiconductive layer that overlies the lower semiconductive layer and adjoins it along an upper semiconductor interface, wherein:

first and second lower buried regions of opposite conductivity types are situated along the lower semiconductor interface;

first and second upper buried regions of opposite conductivity types are situated along the upper semiconductor interface;

the upper semiconductive layer contains a plurality of P-type device regions and a plurality of N-type device regions; and

one of the device regions of each conductivity type laterally meets one of the device regions of the other conductivity type and vertically extends into the upper semiconductive layer to a depth sufficient to meet one of the upper buried regions.

2. A structure as in claim 1 wherein:

each lower buried region vertically extends partway through each of the substrate and the lower semiconductive layer; and

one of the upper buried regions vertically extends partway through each semiconductive layer.

3. A structure as in claim 2 wherein the two lower buried regions are spaced laterally apart from each other along the lower semiconductor interface.

4. A structure as in claim 2 wherein transistor zones are situated in the P-type and N-type device regions.

5. A structure as in claim 2 wherein at least one of each of the P-type and N-type device regions is vertically electrically isolated from the substrate.

6. A structure as in claim 5 wherein each so-isolated device region, including any directly underlying semiconductive material of the same conductivity type as that device region, is surrounded along its outside surface within the semiconductive layers and the substrate by semiconductive material of opposite conductivity type to that device region.

7. A structure as in claim 6 wherein the semiconductive material surrounding one of the so-isolated device regions comprises (a) another of the device regions, (b) a specified one of the upper buried regions, and (c) a specified one of the lower buried regions connected through the lower semiconductive layer to the specified upper buried region.

8. A structure as in claim 5 wherein one of the so-isolated device regions, including any directly underlying semiconductive material of the same conductivity type as that device region, is surrounded along its outside surface within the semiconductive layers and the substrate by a tub of opposite conductivity type to that device region, the tub being surrounded along its outside surface within the semiconductive layers and the substrate by semiconductive material of opposite conductivity type to the tub.

9. A structure as in claim 8 wherein:

the tub comprises (a) another of the device regions, (b) one of the upper buried regions, and (c) one of the lower buried regions; and

the semiconductive material directly surrounding the tub comprises (a) a further one of the device regions and (b) the other lower buried region.

10. A structure as in claim 2 including an N-channel field-effect transistor ("FET") and a P-channel FET, wherein the N-channel FET comprises:

a pair of N-type source/drain zones situated in a first of the P-type device regions and laterally separated from each other by a first channel zone; and

a first gate electrode overlying the first channel zone and vertically separated from the first channel zone by a first gate dielectric layer; and

wherein the P-channel FET comprises;

a pair of P-type source/drain zones situated in a first of the N-type device regions and laterally separated from each other by a second channel zone; and

a second gate electrode overlying the second channel zone and vertically separated from the second channel zone by a second gate dielectric layer.

11. A structure as in claim 10 wherein:

the first P-type device region, including any directly underlying P-type semiconductive material, is surrounded along its outside surface within the semiconductive layers and the substrate by an N-type tub; and

the first N-type device region, including any directly underlying N-type semiconductive material, is surrounded along its outside surface within the semiconductive layers and the substrate by a P-type tub.

12. A structure as in claim 10 further including a PNP transistor and an NPN transistor, wherein the PNP transistor comprises:

an N-type base situated in a second of the P-type device regions;

a P-type emitter situated in the N-type base along its upper surface; and

a P-type collector comprising material of the second P-type device region outside the N-type base; and

wherein the NPN transistor comprises;

a P-type base situated in a second of the N-type device regions;

an N-type emitter situated in the P-type base along its upper surface; and

an N-type collector comprising material of the second N-type device region outside the P-type base.

13. A structure as in claim 12 wherein:

each of the first and second P-type device regions, including any directly underlying P-type semiconductive material, is surrounded along its outside surface within the semiconductive layers and the substrate by an N-type tub; and

each of the first and second N-type device regions, including any directly underlying N-type semiconductive material, is surrounded along its outside surface within the semiconductive layers and the substrate by a P-type tub.

14. A structure as in claim 1 wherein:

each lower buried region vertically extends partway through each of the substrate and the lower semiconductive layer; and

each upper buried region vertically extends partway through each semiconductive layer.

15. A structure as in claim 14 wherein:

the two upper buried regions are spaced laterally apart from each other along the upper semiconductor interface; and

the two lower buried regions are spaced laterally apart from each other along the lower semiconductor interface.

16. A structure as in claim 14 wherein at least one of each of the P-type and N-type device regions is vertically electrically isolated from the substrate.

17. A structure as in claim 16 wherein each so-isolated device region, including any directly underlying semiconductive material of the same conductivity type as that device region, is surrounded along its outside surface within the semiconductive layers and the substrate by semiconductive material of opposite conductivity type to that device region.

18. A structure as in claim 16 wherein one of the so-isolated device regions, including any directly underlying semiconductive material of the same conductivity type as that device region, is surrounded along its outside surface within the semiconductive layers and the substrate by a tub of opposite conductivity type to that device region, the tub being surrounded along its outside surface within the semiconductive layers and the substrate by semiconductive material of opposite conductivity type to the tub.

19. A structure as in claim 18 wherein:

the tub comprises (a) another of the device regions, (b) one of the upper buried regions, and (c) one of the lower buried regions; and

the semiconductive material directly surrounding the tub comprises (a) a further one of the device regions, (b) the other upper buried region, and (c) the other lower buried region.

20. A structure as in claim 19 wherein the lower buried region which forms part of the tub has a sheet resistance of no more than 200 ohms/sq.

21. A structure as in claim 20 further including an additional upper buried region situated along the upper semiconductor interface, the additional upper buried region lying directly below the device region surrounded by the tub and being of the same conductivity type as that device region, the additional upper buried region having a sheet resistance of no more than 1000 ohms/sq.

76. A structure as in claim 8 wherein:

the tub comprises (a) another of the device regions and (b) one of the upper buried regions; and

the semiconductive material directly surrounding the tub comprises (a) a further one of the device regions and (b) one of the lower buried regions.

77. A structure as in claim 18 wherein:

the tub comprises (a) another of the device regions and (b) one of the upper buried regions; and

the semiconductive material directly surrounding the tub comprises (a) a further one of the device regions, (b) the other upper buried region, and (c) one of the lower buried regions.

78. A structure as in claim 18 wherein the tub comprises (a) another of the device regions, (b) one of the upper buried regions, and (c) one of the lower buried regions.

79. A structure as in claim 78 wherein the lower buried region which forms part of the tub has a sheet resistance of no more than 200 ohms/sq.

80. A structure as in claim 79 wherein the other upper buried region lies directly below the device region surrounded by the tub, is of the same conductivity type as that device region, and has a sheet resistance of no more than 1000 ohms/sq.

97. A structure as in claim 2 wherein each device region vertically extends largely through the upper semiconductive layer.

107. A structure as in claim 1 wherein each device region is more lightly doped than the upper buried region of the same conductivity type as that device region.

108. A structure as in claim 107 wherein one of the device regions of each conductivity type laterally meets one of the device regions of the other conductivity type and vertically extends largely through the upper semiconductive layer down to at least one of (a) the upper semiconductor interface and (b) one of the upper buried regions.

22. A semiconductor structure comprising (a) a monocrystalline semiconductive substrate, (b) a lower monocrystalline semiconductive layer that overlies the substrate and adjoins it along a lower semiconductor interface, and (c) an upper monocrystalline semiconductive layer that overlies the lower semiconductive layer and adjoins it along an upper semiconductor interface, wherein:

the substrate comprises a major substrate region of a first conductivity type;

a lower buried region of the first conductivity type more heavily doped than the major substrate region is situated along the lower semiconductor interface and meets the major substrate region;

a lower buried region of a second conductivity type opposite to the first conductivity type is situated along the lower semiconductor interface and meets the major substrate region;

an upper buried region of the first conductivity type is situated along the upper semiconductor interface;

an upper buried region of the second conductivity type is situated along the upper semiconductor interface;

the upper semiconductive layer contains a device region of the first conductivity type and a device region of the second conductivity type laterally meeting the device region of the first conductivity type; and

each device region vertically extends into the upper semiconductive layer to a depth sufficient to meet one of the upper buried regions.

23. A structure as in claim 22 wherein:

the device region of the first conductivity type is more lightly doped than the upper buried region of the first conductivity type and vertically extends through the upper semiconductive layer to meet the upper buried region of the first conductivity type; and

the device region of the second conductivity type vertically extends largely through the upper semiconductive layer.

24. A structure as in claim 23 wherein the upper buried region of the first conductivity type at least partially overlies the lower buried region of the second conductivity type.

25. A structure as in claim 24 wherein the device and upper buried regions of the first conductivity type, including any directly underlying semiconductive material of the first conductivity type, are surrounded along their joint outside surface within the semiconductive layers and the substrate by a tub of the second conductivity type, the tub comprising the device and lower buried regions of the second conductivity type.

26. A structure as in claim 25 including a field-effect transistor that comprises:

a pair of source/drain zones of the second conductivity type situated in the device region of the first conductivity type and laterally separated from each other by a channel zone; and

a gate electrode overlying the channel zone and vertically separated from the channel zone by a gate dielectric layer.

27. A structure as in claim 26 wherein the lower buried region of the second conductivity type has a sheet resistance of no more than 200 ohms/sq.

28. A structure as in claim 27 wherein the upper buried region of the first conductivity type has a sheet resistance of no more than 1000 ohms/sq.

29. A structure as in claim 25 including a bipolar transistor that comprises:

a base of the second conductivity type situated in the device region of the first conductivity type;

an emitter of the first conductivity type situated in the base along its upper surface; and

a collector of the first conductivity type comprising the upper buried region of the first conductivity type and overlying material of the device region of the first conductivity type outside the base.

30. A structure as in claim 25 wherein the upper semiconductive layer further includes an additional device region of the second conductivity type spaced laterally apart from the first-mentioned device region of the second conductivity type, vertically extending largely through the upper semiconductive layer, and at least partially overlying the upper buried region of the first conductivity type.

31. A structure as in claim 30 including a field-effect transistor that comprises:

a source zone of the second conductivity type situated in the device region of the first conductivity type and laterally separated from the additional device region of the second conductivity type by a channel zone;

a main drain zone of the second conductivity type situated in the additional device region of the second conductivity type, more heavily doped than the additional device region, and spaced laterally apart from the channel zone; and

a gate electrode overlying the channel zone, vertically separated from the channel zone by a first dielectric layer, extending over part of the additional device region of the second conductivity type, and vertically separated from the additional device region by a second gate dielectric layer thicker than the first gate dielectric layer.

32. A structure as in claim 25 including a bipolar transistor that comprises:

an emitter of the first conductivity type situated in the additional device region of the second conductivity type along its upper surface;

a base of the second conductivity type comprising material of the additional device region outside the emitter; and

a collector of the first conductivity type comprising the device and upper buried regions of the first conductivity type.

33. A structure as in claim 25 wherein the first and second conductivity types respectively are P type and N type.

34. A structure as in claim 23 wherein the upper semiconductive layer further includes an additional device region of the first conductivity type more lightly doped than the upper buried region of the first conductivity type, spaced laterally apart from the first-mentioned device region of the first conductivity type, and vertically extending largely through the upper semiconductive layer.

35. A structure as in claim 34 including a field-effect transistor that comprises:

a source zone of the first conductivity type is situated in the device region of the second conductivity type and laterally separated from the additional device region of the first conductivity type by a channel zone;

a main drain zone of the first conductivity type situated in the additional device region of the first conductivity type, more heavily doped than the additional device region, and spaced laterally apart from the channel zone; and

a gate electrode overlying the channel zone, vertically separated from the channel zone by a first gate dielectric layer, extending over part of the additional device region of the first conductivity type, and vertically separated from the additional device region by a second gate dielectric layer thicker than the first gate dielectric layer.

36. A structure as in claim 34 including a bipolar transistor that comprises:

an emitter of the second conductivity type situated in the additional device region of the first conductivity type along its upper surface;

a base of the first conductivity type comprising material of the additional device region of the first conductivity type outside the emitter; and

a collector of the second conductivity type comprising the device and lower buried regions of the second conductivity type.

37. A structure as in claim 36 wherein the base further includes an additional upper buried region of the first conductivity type situated along the upper semiconductor interface, spaced laterally apart from the first-mentioned upper buried region of the first conductivity type, more heavily doped than the additional device region of the first conductivity type, and meeting the additional device region.

38. A structure as in claim 23 wherein the lower and upper buried regions of the first conductivity type are electrically connected to each other through the lower semiconductive layer.

39. A structure as in claim 38 including a field-effect transistor that comprises:

a pair of source/drain zones of the second conductivity type situated in the device region of the first conductivity type and laterally separated from each other by a channel zone; and

a gate electrode overlying the channel zone and vertically separated from the channel zone by a gate dielectric layer.

40. A structure as in claim 38 including a capacitor that comprises:

a lower plate of the second conductivity type situated in the device region of the second conductivity type and more heavily doped than the device region of the second conductivity type; and

an upper plate situated above the lower plate and vertically separated from the lower plate by a dielectric layer.

41. A structure as in claim 40 wherein the lower plate overlies the lower buried region of the first conductivity type.

42. A structure as in claim 25 wherein:

the device region of the first conductivity type is more lightly doped than the upper buried region of the first conductivity type and vertically extends through the upper semiconductive layer to meet the upper buried region of the first conductivity type; and

the device region of the second conductivity type is more lightly doped than the upper buried region of the second conductivity type and vertically extends through the upper semiconductive layer to meet the upper buried region of the second conductivity type.

43. A structure as in claim 42 wherein the device and upper buried regions of the first conductivity type at least partially overlie the lower buried region of the second conductivity type.

44. A structure as in claim 43 wherein the device and upper buried regions of the first conductivity type, including any directly underlying semiconductive material of the first conductivity type, are surrounded along their joint outside surface within the semiconductive layers and the substrate by a tub of the second conductivity type, the tub comprising the device, upper buried, and lower buried regions of the second conductivity type.

45. A structure as in claim 44 including a field-effect transistor that comprises:

a pair of source/drain zones of the second conductivity type situated in the device region of the first conductivity type and laterally separated from each other by a channel zone; and

a gate electrode overlying the channel zone and vertically separated from the channel zone by a gate dielectric layer.

46. A structure as in claim 44 including a bipolar transistor that comprises:

a base of the second conductivity type situated in the device region of the first conductivity type;

an emitter of the first conductivity type situated in the base along its upper surface; and

a collector of the first conductivity type comprising the upper buried region of the first conductivity type and overlying material of the device region of the first conductivity type outside the base.

47. A structure as in claim 44 wherein the upper semiconductive layer further includes an additional device region of the second conductivity type more lightly doped than the upper buried region of the second conductivity type, spaced laterally apart from the first-mentioned device region of the second conductivity type, vertically extending largely through the upper semiconductive layer, and at least partially overlying the upper buried region of the first conductivity type.

48. A structure as in claim 47 including a field-effect transistor that comprises:

a source zone of the second conductivity type situated in the device region of the first conductivity type and laterally separated from the additional device region of the second conductivity type by a channel zone;

a main drain zone of the second conductivity type situated in the additional device region of the second conductivity type, more heavily doped than the additional device region, and spaced laterally apart from the channel zone; and

a gate electrode overlying the channel zone, vertically separated from the channel zone by a first dielectric layer, extending over part of the additional device region of the second conductivity type, and vertically separated from the additional device region by a second gate dielectric layer thicker than the first gate dielectric layer.

49. A structure as in claim 47 including a bipolar transistor that comprises:

an emitter of the first conductivity type situated in the additional device region of the second conductivity type along its upper surface;

a base of the second conductivity type comprising material of the additional device region outside the emitter; and

a collector of the first conductivity type comprising the device and upper buried regions of the first conductivity type.

50. A structure as in claim 42 including a bipolar transistor that comprises:

an emitter of the second conductivity type situated in the device region of the first conductivity type along its upper surface;

a base of the first conductivity type comprising the upper buried region of the first conductivity type and overlying material of the device region of the first conductivity type outside the emitter; and

a collector of the second conductivity type comprising the device, upper buried, and lower buried regions of the second conductivity type.

51. A structure as in claim 42 wherein the device and upper buried regions of the second conductivity type, including any directly underlying semiconductive material of the second conductivity type, are surrounded along their joint outside surface within the semiconductive layers and the substrate by a tub of the first conductivity type, the tub comprising the device, upper buried, and lower buried regions of the first conductivity type.

52. A structure as in claim 51 including a bipolar transistor that comprises:

a base of the first conductivity type situated in the device region of the first conductivity type;

an emitter of the second conductivity type situated in the base along its upper surface; and

a collector of the second conductivity type comprising the upper buried region of the second conductivity type and overlying material of the device region of the second conductivity type outside the base.

53. A structure as in claim 22 wherein:

the device region of the first conductivity type vertically extends largely through the upper semiconductive layer; and

the device region of the second conductivity type is more lightly doped than the upper buried layer of the second conductivity type and vertically extends through the upper semiconductive layer to meet the upper buried region of the second conductivity type.

54. A structure as in claim 53 wherein the upper buried region of the second conductivity type at least partially overlies the lower buried region of the first conductivity type.

55. A structure as in claim 54 including a field-effect transistor that comprises:

a pair of source/drain zones of the first conductivity type situated in the device region of the conductivity type and laterally separated from each other by a channel zone; and

a gate electrode overlying the channel zone and vertically separated from the channel zone by a gate dielectric layer.

56. A structure as in claim 54 including a bipolar transistor that comprises:

a base of the first conductivity type situated in the device region of the second conductivity type;

an emitter of the second conductivity type situated in the base along its upper surface; and

a collector of the second conductivity type comprising the upper buried region of the second conductivity type and overlying material of the device region of the second conductivity type outside the base.

57. A structure as in claim 54 including a Schottky diode that comprises:

a cathode comprising the upper buried region of the second conductivity type and directly overlying material of the device region of the second conductivity type; and

an anode directly overlying the device region of the second conductivity type and comprising metal and/or metal-like material.

58. A structure as in claim 53 wherein the lower and upper buried regions of the second conductivity type

are electrically connected to each other through the lower semiconductive layer.

59. A structure as in claim 58 including a field-effect transistor that comprises:

a pair of source/drain zones of the first conductivity type situated in the device region of the second conductivity type and laterally separated from each other by a channel zone; and

a gate electrode overlying the channel zone and vertically separated from the channel zone by a gate dielectric layer.

81. A structure as in claim 25 wherein the tub further includes the upper buried region of the second conductivity type.

98. A structure as in claim 22 wherein:

each lower buried region vertically extends partway through each of the substrate and the lower semiconductive layer; and

one of the upper buried regions vertically extends partway through each semiconductive layer.

99. A structure as in claim 22 wherein:

each lower buried region vertically extends partway through each of the substrate and the lower semiconductive layer; and

each upper buried region vertically extends partway through each semiconductive layer.

109. A structure as in claim 22 wherein each device region is more lightly doped than the upper buried region of the same conductivity type as that device region.

110. A structure as in claim 109 wherein each device region vertically extends largely through the upper semiconductive layer down to at least one of (a) the upper semiconductor interface and (b) one of the upper buried regions.

60. A semiconductor structure comprising (a) a semiconductive substrate, (b) a lower semiconductive layer that overlies the substrate and adjoins it along a lower semiconductor interface, and (c) an upper semiconductive layer that overlies the lower semiconductive layer and adjoins it along an upper semiconductor interface, wherein:

the substrate comprises a major substrate region of a first conductivity type;

a lower buried region of a second conductivity type opposite to the first conductivity type is situated along the lower semiconductor interface and meets the major substrate region;

an upper buried region of the first conductivity type is situated along the upper semiconductor interface and at least partially overlies the lower buried region of the second conductivity type;

an upper buried region of the second conductivity type is situated along the upper semiconductor interface;

a device region of the first conductivity type more lightly doped than the upper buried region of the first conductivity type vertically extends through the upper semiconductive layer to meet the upper buried region of the first conductivity type; and

a device region of the second conductivity type vertically extends largely through the upper semiconductive layer and laterally meets the device region of the first conductivity type.

61. A structure as in claim 60 wherein the device and upper buried regions of the first conductivity type, including any directly underlying semiconductive material of the first conductivity type, are surrounded along their joint outside surface within the semiconductive layers and the substrate by a tub of the second conductivity type, the tub comprising the device and lower buried regions of the second conductivity type.

62. A structure as in claim 61 including a field-effect transistor that comprises:

a pair of source/drain zones of the second conductivity type situated in the device region of the first conductivity type and laterally separated from each other by a channel zone; and

a gate electrode overlying the channel zone and vertically separated from the channel zone by a gate dielectric layer.

63. A structure as in claim 62 wherein:

the lower buried region of the second conductivity type has a sheet resistance of no more than 200 ohms/sq.; and

the upper buried region of the first conductivity type has a sheet resistance of no more than 1,000 ohms/sq.

64. A structure as in claim 61 including a bipolar transistor that comprises:

a base of the second conductivity type situated in the device region of the first conductivity type;

an emitter of the first conductivity type situated in the base along its upper surface; and

a collector of the first conductivity type comprising the upper buried region of the first conductivity type and overlying material of the device region of the first conductivity type outside the base.

65. A structure as in claim 61 wherein an additional device region of the second conductivity type vertically extends largely through the upper semiconductive layer, is spaced laterally apart from the first-mentioned device region of the second conductivity type, and at least partially overlies the upper buried region of the first conductivity type.

66. A structure as in claim 65 including a field-effect transistor that comprises:

a source zone of the second conductivity type situated in the device region of the first conductivity type and laterally separated from the additional device region of the second conductivity type by a channel zone;

a main drain zone of the second conductivity type situated in the additional device region of the second conductivity type, more heavily doped than the additional device region, and spaced laterally apart from the channel zone; and

a gate electrode overlying the channel zone, vertically separated from the channel zone by a first dielectric layer, extending over part of the additional device region of the second conductivity type, and vertically separated from the additional device region by a second gate dielectric layer thicker than the first gate dielectric layer.

67. A structure as in claim 65 including a bipolar transistor that comprises:

an emitter of the first conductivity type situated in the additional device region of the second conductivity type along its upper surface;

a base of the second conductivity type comprising material of the additional device region outside the emitter; and

a collector of the first conductivity type comprising the device and upper buried regions of the first conductivity type.

91. A structure as in claim 61 wherein the device region of the second conductivity type meets the upper buried region of the second conductivity type, the tub further including the upper buried region of the second conductivity type.

92. A structure as in claim 65 wherein the additional device region of the second conductivity type is surrounded along its outside surface within the semiconductive layers and the substrate by a tub of the first conductivity type, the tub of the first conductivity type comprising the device and upper buried regions of the first conductivity type.

100. A structure as in claim 60 wherein:

the lower buried region vertically extends partway through each of the substrate and the lower semiconductive layer; and

one of the upper buried regions vertically extends partway through each semiconductive layer.

101. A structure as in claim 60 wherein:

the lower buried region vertically extends partway through each of the substrate and the lower semiconductive layer; and

each of the upper buried regions vertically extends partway through each semiconductive layer.

102. A structure as in claim 101 wherein the two upper buried regions are spaced laterally apart from each other along the upper semiconductor interface.

111. A structure as in claim 60 wherein the device region of the second conductivity type is more lightly doped than the upper buried region of the second conductivity type.

112. A structure as in claim 111 wherein the device region of the second conductivity type vertically extends through the upper semiconductive layer down to one of the upper buried regions.

68. An integrated semiconductor structure comprising:

a major region of a first conductivity type;

a vertical isolation region of a second conductivity type opposite to the first conductivity type overlying the major region;

a buffer region of the first conductivity type overlying the vertical isolation region; and

a first bipolar transistor that comprises;

a main collector zone of the first conductivity type overlying and meeting the buffer region such that the main collector zone has a higher net peak dopant concentration than the buffer region and such that, where the main collector zone generally meets the buffer region, the net dopant concentration of the buffer region has a different vertical gradient than the net dopant concentration of the main collector zone;

a base zone of the second conductivity type overlying at least part of the main collector zone; and

an emitter zone of the first conductivity type overlying at least part of the base zone.

69. A structure as in claim 68 arranged such that, where the buffer region generally meets the main collector zone, the vertical gradient of the net dopant concentration of the buffer region is less than the vertical gradient of the net dopant concentration of the main collector zone.

70. A structure as in claim 69 further including a lateral isolation region of the second conductivity type laterally surrounding the transistor and meetingthe vertical isolation region so that the two isolation regions provide junction isolation for the transistor laterally and from below.

71. A structure as in claim 70 wherein a further collector zone separates the main collector zone from the lateral isolation region, the further collector zone having a lower net dopant concentration than the main collector zone.

72. A structure as in claim 69 further including a second bipolar transistor of opposite polarity to, and situated laterally with respect to, the first bipolar transistor.

73. A structure as in claim 72 further including:

a first field-effect transistor ("FET") having source/drain zones of the first conductivity type separated by a channel zone in a device region of the second conductivity type; and

a second FET having source/drain zones of the second conductivity type separated by a channel zone situated in a device region of the first conductivity type.

74. A structure as in claim 73 wherein the vertical isolation region provides vertical junction isolation between the major region and the device region of the first conductivity type.

75. A structure as in claim 68 wherein the first and second conductivity types respectively are P-type and N-type.

82. A semiconductor structure comprising (a) a monocrystalline semiconductive substrate, (b) a lower monocrystalline semiconductive layer that overlies the substrate and adjoins it along a lower semiconductor interface, and (c) an upper monocrystalline semiconductive layer that overlies the lower semiconductive layer and adjoins it along an upper semiconductor interface, wherein:

at least one first lower buried region of a first conductivity type is situated along the lower semiconductor interface;

at least one second lower buried region of a second conductivity type opposite to the first conductivity type is situated along the lower semiconductor interface, each second lower buried region being laterally separated from each first lower buried region along the lower semiconductor interface;

at least one first upper buried region of the first conductivity type is situated along the upper semiconductor interface;

at least one second upper buried region of the second conductivity type is situated along the upper semiconductor interface;

the upper semiconductive layer contains a plurality of P-type device regions and a plurality of N-type device regions; and

one of the device regions of each conductivity type laterally meets one of the device regions of the other conductivity type and vertically extends into the semiconductive layer to a depth sufficient to meet one of the upper buried regions.

83. A structure as in claim 82 wherein:

each lower buried region vertically extends partway through each of the substrate and the lower semiconductive layer; and

each first upper buried region vertically extends partway through each semiconductive layer.

84. A structure as in claim 83 wherein transistor zones are situated in the P-type and N-type device regions.

85. A structure as in claim 83 wherein at least one of each of the P-type and N-type device regions is vertically electrically isolated from the substrate.

86. A structure as in claim 85 wherein each so-isolated device region, including any directly underlying semiconductive material of the same conductivity type as that device region, is surrounded along its outside surface within the semiconductive layers and the substrate by semiconductive material of opposite conductivity type to that device region.

87. A structure as in claim 86 wherein the semiconductive material surrounding one of the so-isolated device regions comprises (a) another of the device regions, (b) one specified first upper buried region, and (c) one specified first lower buried region connected through the lower semiconductive layer to the specified first upper buried region.

88. A structure as in claim 85 wherein one of the so-isolated device regions, including any directly underlying semiconductive material of the same conductivity type as that device region, is surrounded along its outside surface within the semiconductive layers and the substrate by a tub of opposite conductivity type to that device region, the tub being surrounded along its outside surface within the semiconductive layers and the substrate by semiconductive material of opposite conductivity type to the tub.

89. A structure as in claim 88 wherein:

the tub comprises (a) another of the device regions, (b) one first upper buried region, and (c) one first lower buried region; and

the semiconductive material directly surrounding the tub comprises (a) a further one of the device regions and (b) one second lower buried region.

90. A structure as in claim 88 wherein:

the tub comprises (a) another of the device regions and (b) one first upper buried region; and

the semiconductive material directly surrounding the tub comprises (a) a further one of the device regions and (b) one second lower buried region.

103. A structure as in claim 83 wherein each second upper buried region vertically extends partway through each semiconductive layer.

104. A structure as in claim 82 wherein each second upper buried region is laterally separated from each first upper buried region along the upper semiconductor interface.

105. A structure as in claim 104 wherein:

each lower buried region vertically extends partway through each of the substrate and the lower semiconductive layer; and

each first upper buried region vertically extends partway through each semiconductive layer.

106. A structure as in claim 105 wherein each second upper buried region vertically extends partway through each semiconductive layer.

113. A structure as in claim 82 wherein each device region is more lightly doped than the upper buried region of the same conductivity type as that device region.

114. A structure as in claim 113 wherein one of the device regions of each conductivity type laterally meets one of the device regions of the other conductivity type and vertically extends largely through the upper semiconductive layer down to at least one of (a) the upper semiconductor interface and (b) one of the upper buried regions.

93. A semiconductor structure comprising (a) a semiconductive substrate, (b) a lower semiconductive layer that overlies the substrate and adjoins it along a lower semiconductor interface, and (c) an upper semiconductive layer that overlies the lower semiconductive layer and adjoins it along an upper semiconductor interface, wherein:

the substrate comprises a major substrate region of a first conductivity type;

a lower buried region of a second conductivity type opposite to the first conductivity type is situated along the lower semiconductor interface and meets the major substrate region;

an upper buried region of the first conductivity type is situated along the upper semiconductor interface and at least partially overlies the lower buried region of the second conductivity type;

a device region of the first conductivity type more lightly doped than the upper buried region of the first conductivity type vertically extends through the upper semiconductive layer to meet the upper buried region of the first conductivity type;

a first device region of the second conductivity type vertically extends largely through the upper semiconductive layer; and

a second device region of the second conductivity type vertically extends largely through the upper semiconductive layer, is spaced laterally apart from the first device region of the second conductivity type, and at least partially overlies the upper buried region of the first conductivity type, the device and upper buried regions of the first conductivity type, including any directly underlying semiconductive material of the first conductivity type, being surrounded along their joint outside surface within the semiconductive layers and the substrate by a tub of the second conductivity type, the tub comprising the first device and lower buried regions of the second conductivity type.

94. A structure as in claim 93 wherein the second device region of the second conductivity type is surrounded along its outside surface within the semiconductive layers and the substrate by a tub of the first conductivity type, the tub of the first conductivity type comprising the device and upper buried regions of the first conductivity type.

95. A structure as in claim 94 including a field-effect transistor that comprises:

a source zone of the second conductivity type situated in the device region of the first conductivity type and laterally separated from the second device region of the second conductivity type by a channel zone;

a main drain zone of the second conductivity type situated in the second device region of the second conductivity type, more heavily doped than the second device region of the second conductivity type, and spaced laterally apart from the channel zone; and

a gate electrode overlying the channel zone, vertically separated from the channel zone by a first dielectric layer, extending over part of the second device region of the second conductivity type, and vertically separated from the second device region of the second conductivity type by a second gate dielectric layer thicker than the first gate dielectric layer.

96. A structure as in claim 94 including a bipolar transistor that comprises:

an emitter of the first conductivity type situated in the second device region of the second conductivity type along its upper surface;

a base of the second conductivity type comprising material of the second device region of the second conductivity type outside the emitter; and

a collector of the first conductivity type comprising the device and upper buried regions of the first conductivity type.