RF power package with a dual ground

• US 5,889,319 A
• Filed: 07/19/1996
• Issued: 03/30/1999
• Est. Priority Date: 07/19/1996
• Status: Expired due to Term

• Current Assignee: Infineon Technologies AG
• Original Assignee: Ericsson, Inc. (Telefonaktiebolaget LM Ericsson)
• Inventors: Leighton, Larry, Moller, Thomas W.
• Primary Examiner(s): CHAUDHURI, OLIK
• Application Number:
  US08/684,474
• Time in Patent Office: 984 Days
• Field of Search: 257/691, 257/732, 257/774, 257/771, 257/776, 257/712, 257/717
• US Class Current: 257/691
• CPC Class Codes: H01L 2223/6644 Packaging aspects of high-frequency amplifiers
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An RF power transistor package is configured for mounting to a heat sink in a multi-layer pc board, and includes a direct top side electrical ground path from a transistor chip located atop a ceramic substrate to a mounting flange, without passing through the ceramic substrate by way of metal plating an outer surface of the ceramic substrate to electrically connect a top mounted metal lead to the flange. A direct ground path from the transistor chip to the mounting flange is also provided by way of plated via holes through the ceramic substrate. The top side ground path is also configured to connect with the middle ground reference layer of the multi-layer pc board when the mounting flange is secured to the heat sink, so that a unified ground potential is seen by the transistor at both the middle layer and heat sink. In this manner, the power transistor package is grounded at the same reference potential as other elements attached to the pc board, while still having the high performance characteristics provided by the ground path via holes.

Claims

1. An RF power transistor package, comprising:

a transistor chip having one or more ground terminals connected to a common ground plane, wherein the transistor chip and common ground plane are each attached to a first surface of a non-conductive substrate;

a conductive mounting flange configured for attachment to a heat sink, wherein a second surface of the non-conductive substrate is attached to the flange, the substrate having a plurality of conductively plated via holes extending between the respective first and second surfaces and forming a first electrical path from the common ground plane to the flange;

a conductive lead coupled to the first surface of the substrate and coupled to the common ground plane; and

a second electrical path connecting the lead to the flange, the second electrical path located external to the non-conductive substrate.

2. The RF power transistor package of claim 1, the flange having a well disposed in a first surface and configured for seating the non-conductive substrate such that a portion of the lead extends from the substrate on a substantially even plane as the flange surface.

3. The RF power transistor package of claim 2, wherein the lead is in direct contact with the flange.

4. The RF power transistor package of claim 1, the second electrical path comprising conductive plating disposed over a third surface of the non-conductive substrate.

5. The RF power transistor package of claim 1, the second electrical path comprising a conductive connector disposed between the respective lead and flange.

6. The RF power transistor package of claim 1, the second electrical path comprising a plurality of conductive connectors disposed between the respective lead and flange.

7. The RF power transistor package of claim 1, the lead configured to make electrical contact with a ground lead disposed on a top surface of a pc board to which the package is attached.

8. An RF power transistor package, comprising:

a transistor chip having one or more ground terminals connected to a common ground plane, wherein the transistor chip and common ground plane are each attached to a first surface of a non-conductive substrate;

a conductive mounting flange configured for attachment to a heat sink, wherein a second surface of the non-conductive substrate is attached to the flange, the substrate having a plurality of conductively plated via holes extending between the respective first and second surfaces and forming a first electrical path from the common ground plane to the flange;

a conductive lead extending from the first surface of the substrate and connected to the common ground plane; and

conductive plating disposed over a third surface of the non-conductive substrate and forming a second electrical path from common ground plane to the flange,

wherein the lead is configured to make electrical contact with a ground lead disposed on a top surface of a pc board to which the package is attached.

9. The RF power transistor package of claim 8, the flange having a well configured for seating the non-conductive substrate such that a portion of the lead extends on a substantially even plane with, and is connected to, respectively, the flange.