Leakage tracking device sample for IDDQ measurement and defect resolution

• US 5,889,409 A
• Filed: 09/27/1996
• Issued: 03/30/1999
• Est. Priority Date: 09/27/1996
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kalb, Jeffrey C. Jr.
• Primary Examiner(s): Ballato, Josie
• Assistant Examiner(s): KOBERT, RUSSELL MARC
• Application Number:
  US08/721,685
• Time in Patent Office: 914 Days
• Field of Search: 324/765, 324/763, 371/21.1, 371/21.2, 371/21.4, 365/201
• US Class Current: 324/750.3
• CPC Class Codes: G01R 31/3004 Current or voltage test
• CPC Class Codes: G01R 31/3008 Quiescent current [IDDQ] test or leakage current test

Abstract

A method for detecting defect in a semiconductor device using IDDQ testing techniques that are not dependent upon the background leakage current for defect resolution. One embodiment of the present invention uses device sampling, i.e. creates a small sample of a device that is representative of the whole device, such that the ratio of the quiescent current of the device to the quiescent current of the sample exhibits a linear relationship to the ratio of the component count of the device to the component count of the sample.

Claims

1. Method for detecting defects in a semiconductor device using a sample of said device comprising the steps of:

setting a screen condition for a device under test;

measuring the quiescent current of said device under test;

measuring the quiescent current of a sample of said device under test, wherein said sample of said device under test is a separate device from said device under test and is a small scale sample of said device under test, and wherein said sample of said device under test and said device under test are located on the same substrate;

determining if the ratio of the quiescent current measurement of said device under test to the quiescent current measurement of said sample of said device under test exceeds said screen condition.

2. The method of claim 1 wherein if said ratio of the quiescent current measurement of said device under test to the quiescent current measurement of said sample of said device under test exceeds said screen condition, then a defect exists in said device under test, and said device under test is determined to be a defective device.

3. The method of claim 1 wherein if said ratio of the quiescent current measurement of said device under test to the quiescent current measurement of said sample of said device under test is less than said screen condition, then no defect exists in said device under test and said device under test, is determined to be a good device.

4. The method as described in claim 1 wherein said sample is built into said device under test.

5. The method of claim 1 where in said sample of said device under test is made up of a selection of components similar to those which make up said device under test, such that said sample is representative of said device under test.

6. The method of claim 1 wherein said sample is matched to said device under test in at least one of the following categories:

device types, vertical device orientation, horizontal device orientation, device width, device length, active areas, active edge lengths, well areas, well edge lengths, gate and cell types, and gate input states.

7. The method of claim 1 wherein said sample is built into said device under test.