Charge-summing digital-to-analog converter

• US 5,889,485 A
• Filed: 09/02/1997
• Issued: 03/30/1999
• Est. Priority Date: 09/02/1997
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Schneider, Edmund Mark
• Primary Examiner(s): YOUNG, BRIAN K
• Application Number:
  US08/922,791
• Time in Patent Office: 574 Days
• Field of Search: 341/172, 341/120, 341/118, 341/144, 341/150, 341/155, 341/154
• US Class Current: 341/150
• CPC Class Codes: H03M 1/68 with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits

Abstract

An integrated circuit includes a digital bus providing a first portion of less significant signals, and a second portion of more significant signals. A digital-to-charge converter connected to the digital bus includes circuitry to convert the less significant portion of the signals to a first charge, and to convert the more significant portion of the signals to a second charge. A charge-to-voltage converter connected to the digital-to-charge converter includes circuitry to convert the first charge to an intermediate voltage. A voltage-to-charge converter connected to the charge-to-voltage converter converts the intermediate voltage to a third charge. A charge-summer connected to the digital-to-charge converter and the voltage-to-charge converter combines the second charge with the third charge to produce a combined charge. The charge-to-voltage converter also is connected to the charge-summer to convert the combined charge to an analog output voltage.

Claims

1. An integrated circuit, comprising:

a digital bus to conduct parallel digital signals including a less significant portion of the signals and a more significant portion of the signals;

digital-to-charge converter connected to the digital bus and including means to convert the less significant portion of the signals to a first charge and to convert the more significant portion of the signals to a second charge;

a charge-to-voltage converter connected to the digital-to-charge converter and including means to convert the first charge to an intermediate analog voltage;

a voltage-to-charge converter connected to the charge-to-voltage converter, to convert the intermediate analog voltage to a third charge;

a charge-summer connected to the digital-to-charge converter and the voltage-to-charge converter, to combine the second charge with the third charge to produce a combined charge; and

in which the charge-to-voltage converter is connected to the charge-summer and further includes means to convert the combined charge to an analog output voltage.

2. The circuit of claim 1, comprising:

a digital bus having multiple lines for corresponding parallel digital signals and including first lines for a less significant portion of the signals and second lines for a more significant portion of the signals;

first control means for generating a multiplexer control signal to select alternatingly the more significant portion of the signals or the less significant portion of the signals;

a transfer bus having at least as many lines for parallel digital signals as the first lines and as many lines as the second lines of the digital bus;

a multiplexer controlled by the first control means and connected to the digital bus and transfer bus to select either the less significant portion and more significant portion of the signals for output onto the transfer bus depending on the multiplexer control signal;

second control means for generating first conversion control signals to regulate the conversion of digital signals to a charge;

a first charge line for carrying a charge;

a digital-to-charge converter controlled by the second control means and connected to the transfer bus, and the charge line for converting the digital signals on the transfer bus into a first charge signal transmitted onto the charge line depending on the first conversion signal;

third control means for generating second conversion control signals to regulate the conversion of charge to voltage;

an analog voltage line;

a charge-to-voltage converter controlled by the third control means and connected to the first charge line and voltage line to convert the charge of the first charge line into an analog voltage which is output onto the voltage line depending on the second conversion signal;

fourth control means for generating third conversion control signals to regulate the conversion of the voltage resulting from the less significant portion of digital signals into a charge for the less significant portion of the signals;

a second charge line for carrying a charge;

a voltage-to-charge converter connected to the voltage line and second charge line to convert an analog voltage for the less significant portion of the signals to a second charge for the less significant portion of the signals output onto the second charge line depending on the third conversion signal; and

summing means connected to the first and second charge lines for combining a third charge resulting from converting the more significant portion of signals with the second charge produced from the less significant portion of signals and outputting the combined charge; and

in which the charge-to-voltage converter also is connected to the summing means to convert the combined charge into an analog voltage which is output onto the voltage line depending on the second conversion signal.

3. The circuit of claim 2 in which:

the second, third, and fourth control means consist of a clocking generator circuit including a multi-phase, non-overlapping clock generator and the first, second, and third control signal means consist of multi-phase non-overlapping clock signals;

the multiplexer includes from 3 to 8 multiplexing circuits, each connected to a respective signal line of each portion of multiple parallel lines of the digital bus;

the digital-to-charge converter includes;

a source of a first reference voltage;

a charge distribution line;

a switch to connect/disconnect the charge distribution line with the source of a first reference voltage;

a source of a second reference voltage;

a voltage distribution line;

a switch to connect/disconnect the voltage distribution line from the source of a second reference voltage;

a plurality of binaurally weighted conversion capacitors including one of a minimum size to provide resolution with respect to noise or manufacturability, with a first plate connected to the voltage distribution line;

a switch in series with each respective conversion capacitor, connected between a second plate of each respective capacitor and the charge distribution line, and each switch controlled by a different line of the transfer bus to control the setting of the respective switch;

input switches to connect the first reference voltage to the voltage distribution line and the second reference voltage to the charge distribution line to charge the conversion capacitors and to disconnect the sources of voltage from the digital-to-charge converter when charge is output to the charge-to-voltage converter; and

output switches to connect the charge distribution line and voltage distribution line to respective inputs of the charge-to-voltage converter and a to disconnect the charge and voltage distribution lines from the charge-to-voltage converter when the conversion capacitors are being recharged;

the sources of first and second reference voltage include respective voltage-multiplexers connected to a source of high reference voltage, a source of low reference voltage, and a sign bit line with a sign signal to control switching between;

a first state in which the source of first reference voltage is connected to the source of high reference voltage and the source of second reference voltage is connected to a source of low reference voltage;

and a second state in which the source of first reference voltage is connected to the source of low reference voltage and the source of second reference voltage is connected to the source of high reference voltage; and

the digital-to-charge converter further includes a capacitor of the minimum size, with one plate connected to the voltage distribution line and the other plate connected through two switches to the charge distribution line and with a control input of one switch connected to the sign bit and the control input of the other switch connected to the third control means;

the charge-to-voltage converter includes;

an operational amplifier with a negative input terminal, a positive input terminal, and an output terminal;

an integration capacitor between the negative input terminal and output terminal of the amplifier; and

a switch between the negative input terminal and output terminal of the amplifier, electrically in parallel with the integration capacitor;

the voltage-to-charge converter includes;

a sampling capacitor;

an input switch for connecting the capacitor to the analog voltage line to charge the sampling capacitor when the charge-to-voltage converter is outputting an analog voltage for the less significant word, and for isolating the sampling capacitor from the output voltage when the conversion capacitors are being recharged; and

an output switch for connecting the sampling capacitor to the input of the charge-to-voltage converter when controlling the digital-to-charge converter to output a charge for the more significant portion of the signals, and for isolating the sampling capacitor when controlling the digital-to-charge converter to recharge the conversion capacitors; and

the summing means is a junction between the output of the voltage-to-charge converter and the output of the digital-to-charge converter.

4. The circuit of claim 1, comprising:

a first bus having multiple lines for corresponding parallel digital signals for a less significant portion of the signals;

a second bus having multiple lines for corresponding parallel digital signals for a more significant portion of the signals;

a first digital-to-charge converter connected to the first bus to convert the signals of the less significant portion of the digital signals to a first charge;

a first charge-to-voltage converter connected to the first digital-to-charge converter to convert the first charge into a first analog voltage;

a voltage-to-charge converter to convert the first analog voltage to a second charge;

a second digital-to-charge converter connected to the second bus to convert the signals of the more significant portion of the digital signals to a third charge;

summing means connected with the voltage-to-charge converter and the second digital-to-charge converter, for combining the second charge with the third charge to produce a combined charge; and

a second charge-to-voltage converter connected to the summing means to convert the combined charge into an output analog voltage.

14. The integrated circuit of claim 1 wherein said digital to charge converter includes n/2 capacitors.

15. The integrated circuit of claim 1 wherein both said first and second subsets of n bits is comprised of n/2 bits.

16. The integrated circuit of claim 1 wherein said digital to analog converter is an n/2 bit digital to analog converter.

5. A process for operating a circuit, comprising:

converting parallel digital signals of a less significant portion of the signals to a first charge;

converting the first charge to a first analog voltage;

converting the first analog voltage to a second charge;

converting the parallel digital signals of a more significant portion of the signals to a third charge;

combining the second charge with the third charge to form a combined charge;

converting the combined charge to a second analog voltage; and

transmitting the second analog voltage.

6. The process of claim 5 in which:

the step of converting the less significant portion of the digital signals to a first charge includes the steps of;

charging a set of binaurally weighted capacitors to provide respective binaurally weighted charges;

controlling the setting of a respective switch for each capacitor depending on the signals of the less significant portion; and

redistributing the charges of the capacitors in a charge output line, depending on the setting of the switches;

the process further comprises the steps of;

switching a reference voltage for charging the capacitors depending on the value of a sign bit signal;

setting switches to select the less significant portion of the digital signals prior to the step of converting the less significant portion of the signals to the first charge and then resetting switches to select the more significant portion of the signals prior to converting the more significant portion of the signals to the third charge; and

converting parallel signals of a less significant portion of the digital signals to a first charge.

7. A process for producing an integrated circuit, comprising the steps of:

providing a bus for digital signals;

providing a digital-to-charge converter including means to convert a less significant portion of the signals to a first charge and to convert a more significant portion of the signals to a second charge;

providing a charge-to-voltage converter including means to convert the first charge to an intermediate analog voltage and to convert a combined charge to an analog output voltage;

providing a voltage-to-charge converter including means to convert the intermediate analog voltage to a third charge; and

providing a charge-summer including means to combine the first charge with the third charge to produce the combined charge.

8. An integrated circuit that outputs an analog signal based on an inputted digital signal having n bits, said circuit comprising:

a multiplexor device for receiving said n bits and sequentially outputting a first subset of said n bits, and then outputting a second subset of said n bits;

a digital to analog converter that, in sequence, converts said first subset of said n bits from said multiplexor into a first analog signal, and then converts said second subset of said n bits from said multiplexor into a second analog signal;

a scaling mechanism that scales said first analog signal; and

a summing mechanism that sums said scaled first analog signal and said second analog signal.

9. The integrated circuit of claim 8 wherein said first subset of said n bits is a least significant portion of the digital signal.

10. The integrated circuit of claim 9 wherein said first subset of said n bits is a most significant portion of the digital signal.

11. The integrated circuit of claim 10 wherein said scaling mechanism divides said least significant portion of the digital signal by a scaling factor.

12. The integrated circuit of claim 8 wherein said digital to analog converter comprises:

a digital to charge converter; and

a charge to voltage converter.

13. The integrated circuit of claim 12 wherein said summing mechanism comprises:

a voltage to charge converter, said voltage to charge converter being coupled to an output of said charge to voltage converter; and

a charge summer coupled to an output of said voltage to charge converter, said charge summer being coupled between said digital to charge converter and said charge to voltage converter.