Method of generating layout of semiconductor integrated circuit

• US 5,889,681 A
• Filed: 10/30/1996
• Issued: 03/30/1999
• Est. Priority Date: 10/31/1995
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Suda, Motomu
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): GARBOWSKI, LEIGH M
• Application Number:
  US08/739,831
• Time in Patent Office: 881 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491
• US Class Current: 716/122
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

A method of generating a hierarchical layout of cells of a semiconductor integrated circuit includes the steps of arranging an abstract cell in a target cell, setting the positions of second terminals in the abstract cell as compaction constraints on first terminals of the target cell, forming jogged lines, moving the first terminals having the compaction constraints to intersections between the jogged lines and an edge of the abstract cell, and compacting the target cell.

Claims

1. A method of generating a layout of cells of a semiconductor integrated circuit, comprising the steps of:

selecting, among a plurality of terminals which have not been connected, a first terminal as one end of a wiring for connection and a second terminal to be connected to said first terminal through said wiring;

arranging an abstract cell in a position of a plurality of layout objects connected to said second terminal in order that said second terminal is located at an edge of said abstract cell, said layout objects being included by said abstract cell;

removing said layout objects and said second terminal;

reducing the size of said abstract cell to form a virtual channel area;

setting the positions of said second terminals on the abstract cell as compaction constraints on the first terminals;

extending said wiring with a jogged line from the first terminals to reach the edge of the abstract cell through said virtual channel area;

moving the first terminals having the compaction constraints to intersections between the jogged line and the edge of the abstract cell;

compacting said layout; and

replacing said abstract cell with the plurality of said layout objects.

2. The method of claim 1, wherein, if there are breaks between the first and second terminals after compacting the target cell, the breaks are zeroed by repeating the steps of:

comparing the positions of each pair of the first and second terminals on the edge of the abstract cell, to determine a direction from the first terminal to the second terminal;

reducing the size of the abstract cell, to form a virtual channel area;

setting the positions of the second terminals on the abstract cell as compaction constraints on the first terminals and setting a compact size as a compaction constraint on the abstract cell;

extending jogged lines from the first terminals toward the second terminals through the virtual channel area according to the determined directions;

moving the first terminals having the compaction constraints to intersections between the jogged lines and the edge of the abstract cell; and

compacting the target cell.

3. A method of generating a layout of cells of a semiconductor integrated circuit, comprising the steps of:

selecting, among a plurality of terminals which have not been connected, a first terminal as one end of a wiring for connection and a second terminal to be connected to said first terminal through said wiring;

arranging an abstract cell in a position of a plurality of layout objects including said second terminal in order that said second terminal is located at an edge of said abstract cell;

setting the positions of said second terminals on the abstract cell as compaction constraints on the first terminals;

extending said wiring with a jogged line from the first terminals to reach the edge of the abstract cell;

moving the first terminals having the compaction constraints to intersections between the jogged line and the edge of the abstract cell;

compacting said layout; and

repeating the above steps.

4. A storage medium storing an electrically readable program that generates a layout of cells of a semiconductor integrated circuit through the steps of:

selecting, among the cells, a target cell having a lower cell and replacing the lower cell with an abstract cell whose periphery is identical to that of an uncompacted form of the lower cell and which has terminals whose positions agree with those of the uncompacted form of the lower cell;

reducing the size of the abstract cell, to form a virtual channel area after the lower cell is replaced with the abstract cell;

setting the positions of the terminals on the lower cell after compaction as compaction constraints on the terminals of the abstract cell, to properly connect the target and lower cells to each other, and setting a compact size of the lower cell as a compaction constraint on the abstract cell;

extending jogged lines from the terminals of the abstract cell up to an edge of the reduced abstract cell through the virtual channel area after the compaction constraints have been set;

moving the terminals of the abstract cell having the compaction constraints to intersections between the jogged lines and the edge of the reduced abstract cell; and

compacting the target cell.

5. The method of claim 4, further comprising the step of repeating the steps recited in claim 4 from the lowest hierarchical level to the highest hierarchical level.

6. A method of generating a hierarchical layout of cells of a semiconductor integrated circuit from a lowest cell up to a highest cell, comprising the steps of:

selecting, among the cells, a target cell having a lower cell and replacing the lower cell with an abstract cell whose periphery is identical to that of an uncompacted form of the lower cell and which has terminals whose positions agree with those of the uncompacted form of the lower cell;

reducing the size of the abstract cell, to form a virtual channel area after the lower cell is replaced with the abstract cell;

setting the positions of the terminals on the lower cell after compaction as compaction constraints on the terminals of the abstract cell, to properly connect the target and lower cells to each other, and setting a compact size of the lower cell as a compaction constraint on the abstract cell;

extending jogged lines from the terminals of the abstract cell up to an edge of the reduced abstract cell through the virtual channel area after the compaction constraints have been set;

moving the terminals of the abstract cell having the compaction constraints to intersections between the jogged lines and the edge of the reduced abstract cell;

compacting the target cell; and

replacing the abstract cell with the lower cell of the compact size.

7. The method of claim 6, further comprising the step of repeating the steps recited in claim 6 from the lowest hierarchical level to the highest hierarchical level.

8. The method of claim 6, wherein, if there are breaks between the target and lower cells after compacting the target cell, the breaks are zeroed by repeating the steps of:

comparing the positions of each pair of the terminals of the abstract and lower cells on the edge of the abstract cell, to determine a direction from the terminal of the abstract cell to the terminal of the lower cell;

reducing the size of the abstract cell, to form a virtual channel area;

setting the positions of the terminals of the lower cell as compaction constraints on the terminals of the abstract cell, to connect the target and lower cells to each other and setting a compact size of the lower cell as a compaction constraint on the abstract cell;

extending jogged lines from the terminals of the abstract cell toward the edge of the reduced abstract cell through the virtual channel area according to the determined directions;

moving the terminals of the abstract cell having the compaction constraints to intersections between the jogged lines and the edge of the reduced abstract cell; and

compacting the target cell.

9. The method of claim 6, wherein lines of the target cell are constrained so that they are connected to the terminals of the abstract cell, and the terminals of the target cell are constrained to be movable within a given range.

10. The method of claim 6, wherein the positions of the terminals of the abstract cell are determined according to the shapes of lines of the target and lower cells to be connected to each other.

11. A storage medium storing an electrically readable program that generates a layout of cells of a semiconductor integrated circuit through the steps of:

selecting, among a plurality of terminals which have not been connected, a first terminal as one end of a wiring for connection and a second terminal to be connected to said first terminal through said wiring;

arranging an abstract cell in a position of a plurality of layout objects connected to said second terminal in order that said second terminal is located at an edge of said abstract cell, said layout objects being included by said abstract cell;

removing said layout objects and said second terminal;

reducing the size of said abstract cell to form a virtual channel area;

setting the positions of said second terminals on the abstract cell as compaction constraints on the first terminals;

extending said wiring with a jogged line from the first terminals to reach the edge of the abstract cell through said virtual channel area;

moving the first terminals having the compaction constraints to intersections between the jogged line and the edge of the abstract cell;

compacting said layout; and

replacing said abstract cell with the plurality of said layout objects.

12. A storage medium storing an electrically readable program that generates a layout of cells of a semiconductor integrated circuit through the steps of:

selecting, among a plurality of terminals which have not been connected, a first terminal as one end of a wiring for connection and a second terminal to be connected to said first terminal through said wiring;

arranging an abstract cell in a position of a plurality of layout objects connected to said second terminal in order that said second terminal is located at an edge of said abstract cell, said layout objects being included by said abstract cell;

setting the positions of said second terminals on the abstract cell as compaction constraints on the first terminals;

extending said wiring with a jogged line from the first terminals to reach the edge of the abstract cell;

moving the first terminals having the compaction constraints to intersections between the jogged line and the edge of the abstract cell; and

compacting said layout.