Standby voltage boosting stage and method for a memory device

• US 5,889,723 A
• Filed: 03/27/1997
• Issued: 03/30/1999
• Est. Priority Date: 03/29/1996
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: SGS-Thomson Microelectronics, S.R.L. (STMicroelectronics NV)
• Inventors: Pascucci, Luigi
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US08/826,008
• Time in Patent Office: 733 Days
• Field of Search: 365/229, 365/226
• US Class Current: 365/229
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps

Abstract

A voltage booster stage including a voltage booster circuit; a generating circuit generating an enabling signal enabling the voltage booster circuit; and a control circuit controlling the generating circuit. The control circuit receives a standby signal, and generate an operating mode signal having a first value indicating a voltage boost operating mode, and a second value indicating a supply voltage operating mode. The generating circuit receives the operating mode signal and the standby signal, and generates the enabling signal enabling the voltage booster circuit in the presence of the standby signal and the first value of the operating mode signal.

Claims

1. A standby voltage boosting circuit, for a memory device having a supply voltage, comprising:

a voltage booster circuit to receive the supply voltage and to provide a boosted voltage higher than the supply voltage for use in active operation of the device, the voltage booster circuit having a first input;

a generating circuit, having a first input to receive a standby signal, a second input to receive an operating mode signal, and a first output coupled to the voltage booster circuit input, to generate a first control signal on the first output; and

a control circuit, having an input to receive the standby signal, the control circuit including an operating mode detecting circuit having an output to provide the operating mode signal, the operating mode signal having a first value indicating a voltage boost operating mode, and a second value indicating a supply voltage operating mode.

2. The circuit of claim 1, further comprising a first memory circuit, coupled to the generating circuit, to store a first work frequency signal of the voltage booster circuit.

3. The circuit of claim 2, wherein the voltage booster circuit includes at least one booster stage, the booster stage comprising:

a first reference potential line;

an output line;

a capacitive element having a first terminal and a second terminal;

a first switching circuit coupled to the first terminal of the capacitive element and to the first reference potential line;

a second switching circuit coupled to the first terminal of the capacitive element and to the output line; and

a drive circuit, connected to the second terminal of the capacitive element, to switch the second terminal between a first voltage value and a second voltage value, the drive circuit including a first logic circuit and a second logic circuit, the first logic circuit being coupled in parallel with the second logic circuit, the first logic circuit presenting to a first switching speed for the voltage at the second terminal of the capacitive element, the second logic circuit presenting a second switching speed for the voltage at the second terminal of the capacitive element, the first and the second switching speeds having different values.

4. The circuit of claim 3, wherein:

the first logic circuit comprises a first controlled switch having a control input and a second controlled switch having a control input;

the second logic circuit comprises a third controlled switch having a control input and a fourth controlled switch having a control input;

the first output of the generating circuit is coupled to the control input of the first controlled switch and to the control input of the second controlled switch; and

the generating circuit further comprises a second output to provide a second control signal, the second output being coupled to the control input of the third controlled switch and to the control input of the fourth controlled switch.

5. The circuit of claim 4, wherein:

the first logic circuit further comprises an inverting element coupled to the first reference potential line through the first controlled switch and to a second reference potential line through the second controlled switch; and

the second logic circuit further comprises an inverting element coupled to the first reference potential line through the third controlled switch and to the second reference potential line through the fourth controlled switch.

6. The circuit of claim 4, wherein:

the first memory circuit comprises

a first nonvolatile element to store a value of the first work frequency signal, and

a second nonvolatile element to store a value of a second work frequency signal; and

the generating circuit further comprises a third logic circuit to the first nonvolatile element and the second nonvolatile element and to the first and second outputs of the generating circuit, the third logic circuit to generate the first control signal in response to values of the standby signal and the first work frequency signal, and to generate the second control signal in response to values of the standby signal and the second work frequency signal.

7. The circuit of claim 6, wherein the third logic circuit comprises an enabling circuit having an input to receive the standby signal, to generate the first control signal and the second control signal based on stored values of the first nonvolatile memory element and the second nonvolatile memory element when the standby signal indicates that the voltage booster circuit is to operate in a standby mode.

8. The circuit of claim 2, further comprising a second memory circuit coupled to the operating mode detecting circuit to store a value of the operating mode signal.

9. The circuit of claim 8, wherein:

the second memory circuit has an output to supply a mode storage signal;

the operating mode detecting circuit has a first input to receive a voltage level signal, a second input to receive the standby signal, and a third input coupled to the output of the second memory circuit to receive the mode storage signal; and

the operating mode detecting circuit comprises

a first logic circuit coupled to the first input, the second input and the output of the operating mode detecting circuit, to provide the first value of the operating mode signal for a predetermined value of the voltage level signal and when the standby signal indicates that the memory device is operating in a standby mode of operation, and

a second logic circuit coupled to the second input, the third input and the output of the operating mode detecting circuit, to provide the first value of the operating mode signal for a predetermined value of the mode storage signal and when the standby signal indicates that the memory device is operating in a normal mode of operation.

10. The circuit of claim 9, wherein the operating mode detecting circuit further comprises:

a fourth input to receive an operation disabling signal; and

a third logic circuit coupled to the fourth input and to the output of the operating mode detecting circuit to generate the second value of the operating mode signal when the operation disable signal has a predetermined value.

11. The circuit of claim 8, further comprising:

a first controlled switch operable in response to the standby signal;

a second controlled switch, operable in response to the output of the operating mode detection circuit;

a third controlled switch operable in response to the standby signal;

a fourth controlled switch, operable in response to the output of the operating mode detection circuit and having an opposite phase of operation from operation of the second controlled switch; and

wherein the second memory circuit comprises a flip-flop circuit having a first input coupled to the first controlled switch and to the second controlled switch and a second input coupled to the third controlled switch and the fourth controlled switch.

12. A standby voltage boosting method, for a memory device having a supply voltage, comprising steps of:

generating an operating mode signal to have a first value indicating a voltage boost operating mode, and a second value indicating a supply voltage operating mode;

generating a standby signal to have one of a first value and a second value; and

generating a control signal, for controlling a voltage booster circuit when the standby signal and the operating mode signal have predetermined values the voltage booster circuit to supply a boosted voltage higher than the supply voltage. the boosted voltage for use in actively operating the memory device.

13. The method of claim 12, further comprising steps of:

providing the voltage booster circuit, the voltage booster circuit comprising

at least one booster stage, and

a switching circuit having

a first logic circuit to operate the voltage booster circuit at a first switching speed, and

a second logic circuit, coupled in parallel with the first logic circuit, to operate the voltage booster circuit at a second switching speed;

storing a first work frequency signal; and

enabling operation of at least one of the first logic circuit and the second logic circuit on the basis of the first work frequency signal.

14. A method as claimed in claim 12, further comprising steps of:

providing the voltage booster circuit, the voltage booster circuit comprising

at least one booster stage, and

a switching circuit having

a first logic circuit to operate the voltage booster circuit at a first switching speed, and

a second logic circuit, coupled in parallel with the first logic circuit, to operate the voltage booster circuit at a second switching speed;

storing a first work frequency signal;

storing a second work frequency signal;

enabling operation of the first logic circuit in response to values of the standby signal and the first work frequency signal; and

enabling operation of the second logic circuit in response to values of the standby signal and the second work frequency signal.

15. The method of claim 14, further comprising a step of:

enabling operation of the first logic circuit and the second logic circuit when the operating mode signal has the first value and in response to the standby signal.

16. The method of claim 12, further comprising a step of storing the operating mode signal.

17. A method as claimed in claim 16, further comprising steps of:

generating a stored mode signal;

providing a voltage level signal;

generating the first level of the operating mode signal based on the voltage level signal when the standby signal has a first value; and

generating the first level of the operating mode signal based on the stored mode signal when the standby signal has a second value.

18. The method of claim 17, further comprising steps of:

providing an operation disabling signal; and

generating the second level of the operating mode signal in response to the operation disabling signal.

19. A method of operating a voltage boosting circuit for a device, the voltage boosting circuit being operable in a boosting mode and a standby mode, comprising steps of:

detecting when the device is operating in a device boost mode, the device potentially requiring voltage boosting during operation of the device in the device boost mode;

disabling operation of the voltage boosting circuit when the device is not operating in the device boost mode; and

enabling operation of the voltage boosting circuit when the device is not operating in the device boost mode.

20. The method of claim 19, wherein the device comprises a memory circuit and the detecting step comprises a step of:

sensing when a supply voltage of the device is low.

21. The method of claim 19, wherein the detecting step comprises a step of:

sensing when the voltage boosting circuit is operating in the boosting mode; and

storing a value corresponding to operation of the voltage boosting circuit in the boosting mode.

22. The method of claim 19, further comprising steps of:

operating the voltage boosting circuit at a first frequency during standby mode when the device is operating in the device boost mode; and

operating the voltage boosting circuit at a second frequency during boosting mode when the device is operating in the device boost mode.

23. The method of claim 22, further comprising a step of:

determining the first frequency based on a first stored value.

24. The method of claim 22, further comprising a step of:

determining the first frequency based on a plurality of stored values.

25. A voltage boosting circuit for a device, comprising:

a voltage pump circuit;

means for detecting when the device is operating in a device boost mode, the device potentially requiring voltage boosting during operation of the device in the device boost mode;

means for disabling operation of the voltage pump circuit when the device is not operating in the device boost mode; and

means for enabling operation of the voltage pump circuit when the device is not operating in the device boost mode.

26. The circuit of claim 25, wherein the means for detecting comprises:

means for sensing when the voltage boosting circuit is operating in the boosting mode; and

a storage element, coupled to the means for sensing, to store a value corresponding to operation of the voltage boosting circuit in boosting mode.

27. The circuit of claim 25, further comprising:

means for operating the voltage pump circuit at a first frequency, during standby mode when the device is operating in the device boost mode; and

means for operating the voltage pump circuit at a second frequency during boosting mode when the device is operating in the device boost mode.

28. The circuit of claim 27, further comprising:

means for determining the first frequency based on a first stored value.

29. The circuit of claim 28, wherein the voltage pump circuit comprises

a plurality of voltage boosting stage circuits, each comprising

a voltage boosting element,

a first drive circuit, coupled to the voltage boosting element, to drive the voltage boosting element at a first frequency, and

a second drive circuit, coupled to the voltage boosting element, to drive the voltage boosting element at a second frequency;

and

the means for determining the first frequency comprises a logic circuit coupled to the storage element and the first drive circuit.

30. A method of operating a voltage boosting circuit operable in a boosting mode and a standby mode, the method comprising steps of:

storing a first frequency value;

operating the voltage boosting circuit at a standby frequency during the standby mode, the standby frequency being responsive to the first frequency value; and

operating the voltage boosting circuit at a boosting frequency during the boosting mode of operation.

31. The method of claim 30, wherein the boosting frequency is a maximum frequency of operation for the boosting circuit.

32. The method of claim 30, further comprising a step of storing a second frequency value, and wherein the standby frequency is responsive to the first frequency value and the second frequency value.

33. The method of claim 32, wherein the voltage boosting circuit comprises:

a plurality of voltage boosting stage circuits, each comprising

a voltage boosting element,

a first drive circuit, coupled to the voltage boosting element, to drive the voltage boosting element at a first frequency, and

a second drive circuit, coupled to the voltage boosting element, to drive the voltage boosting element at a second frequency; and

the step of operating the voltage boosting circuit at the standby frequency comprises a step of selectively enabling one of;

the first drive circuit, the second drive circuit, both the first drive circuit and the second drive circuit and neither the first drive circuit nor the second drive circuit.

34. The method of claim 33, further comprising a step of:

selectively disabling the voltage boosting circuit when the operating parameters of a device coupled to the voltage boosting circuit indicate that voltage boosting will not be required.

35. A voltage boosting circuit for a device, the voltage boosting circuit being operable in a boosting mode and a standby mode, comprising:

a voltage pump circuit;

a storage element to store a first frequency value;

means for operating the voltage pump circuit at a standby frequency, coupled to the storage element, the standby frequency being responsive to the first frequency value during the standby mode; and

means for operating the voltage pump circuit at a boosting frequency during the boosting mode of operation.

36. The circuit of claim 35, further comprising a storage element to store a second frequency value, coupled to the means for operating the voltage pump circuit at a standby frequency;

and

wherein the standby frequency is responsive to the first frequency value and the second frequency value.

37. The circuit of claim 36, wherein the voltage pump circuit comprises:

a plurality of voltage boosting stage circuits, each comprising

a voltage boosting element,

a first drive circuit, coupled to the voltage boosting element, to drive the voltage boosting element at a first frequency, and

a second drive circuit, coupled to the voltage boosting element, to drive the voltage boosting element at a second frequency; and

the means for operating the voltage pump circuit at the standby frequency comprises a means for selectively enabling one of;

the first drive circuit, the second drive circuit, both the first drive circuit and the second drive circuit and neither the first drive circuit nor the second drive circuit.

38. The circuit of claim 37, further comprising:

means for selectively disabling the voltage pump circuit when the operating parameters of the device indicate that voltage boosting will not be required.

39. A standby pump circuit, comprising:

a plurality of voltage boosting stage circuits, each comprising

a voltage boosting element,

a first drive circuit, coupled to the voltage boosting element, to drive the voltage boosting element at a first frequency, and

a second drive circuit, coupled to the voltage boosting element, to drive the voltage boosting element at a second frequency; and

a selection circuit to selectively enable operation of the first drive circuit and the second drive circuit.

40. The standby pump circuit of claim 39, wherein the first drive circuit is coupled to the second driving circuit in parallel.

41. The standby pump circuit of claim 39, wherein the first frequency and the second frequency are different.

42. The standby pump circuit of claim 39, wherein the selection circuit includes a circuit to enable the first drive circuit and the second drive circuit at the same time, to drive the voltage boosting element at a third frequency.

43. The standby pump circuit of claim 42, wherein the first frequency, second frequency and third frequency each have different values.

44. A standby voltage boosting circuit for a non-volatile memory device having a supply voltage, comprising:

a voltage booster circuit to receive the supply voltage and to provide a boosted voltage higher than the supply voltage for use in active operation of the device, the voltage booster circuit having a first input;

a generating circuit, having a first input to receive a standby signal, a second input to receive an operating mode signal, and a first output coupled to the voltage booster circuit input, to generate a first control signal on the first output; and

a control circuit, having an input to receive the standby signal, the control circuit including an operating mode detecting circuit having an output to provide the operating mode signal, the operating mode signal having a first value indicating a voltage boost operating mode, and a second value indicating a supply voltage operating mode.

45. A standby voltage boosting method for a non-volatile memory device having a supply voltage, comprising steps of:

generating an operating mode signal to have a first value indicating a voltage boost operating mode, and a second value indicating a supply voltage operating mode;

generating a standby signal to have one of a first value and a second value; and

generating a control signal, for controlling a voltage booster circuit when the standby signal and the operating mode signal have predetermined values the voltage booster circuit to supply a boosted voltage higher than the supply voltage, the boosted voltage for use in actively operating the memory device.