Method and apparatus for distributing an optical clock in an integrated circuit

• US 5,889,903 A
• Filed: 05/14/1998
• Issued: 03/30/1999
• Est. Priority Date: 12/31/1996
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Rao, Vallur R.
• Primary Examiner(s): Healy, Brian
• Application Number:
  US09/079,497
• Time in Patent Office: 320 Days
• Field of Search: 385/14, 385/15, 385/24, 385/27, 385/31, 385/39, 385/42, 385/43, 385/44, 385/45, 385/46, 385/50, 385/88, 385/89, 250/227.11, 250/227.12, 250/227.28, 327/291, 327/292, 327/293, 327/294
• US Class Current: 385/14
• CPC Class Codes: G02B 6/43 Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
• CPC Class Codes: G06F 1/105 in which the distribution is at least partially optical

Abstract

A method and an apparatus for optically clocking an integrated circuit in a semiconductor. In one embodiment, a laser is configured to emit infrared laser pulses at a desired clock frequency. The laser pulses are separated into a plurality of split laser pulses, each of which are focused through the back side of a C4 packaged integrated circuit die into P-N junctions distributed throughout the integrated circuit die. Each P-N junction locally generates a photocurrent in response to the split laser beams. Each of the photocurrents are locally converted into voltages and thus into local clock signals, which are used to clock the local area of the integrated circuit. With the presently described optical clocking technique, the local clock signals have extremely low clock skew. The presently described technique may be employed in integrated circuits system-wide, in multi-chip modules, or in an individual integrated circuit. By removing the global clock distribution network from the silicon, the present invention allows chip area used in the prior art for a global clock distribution networks to be used instead for signal routing or allows overall die sizes to be reduced.

Claims

1. An optical clock distribution network, comprising:

a first photo detector disposed in a first semiconductor having at least a front side and a back side, the first photo detector configured to receive laser pulses through the back side of the first semiconductor; and

a first current to voltage converter coupled to the first photo detector, the first current to voltage converter to generate a first clock signal to clock a first area of an integrated circuit disposed in the first semiconductor.

2. The optical clock distribution network described in claim 1 further comprising a first buffer coupled between the first current to voltage converter and the first area of the integrated circuit.

3. The optical clock distribution network described in claim 1 wherein the first semiconductor includes portions that define a recess in the back side of the first semiconductor proximate to the first photo detector, the recess reducing attenuation of the laser pulses through the back side of the first semiconductor into the first photo detector.

4. The optical clock distribution network described in claim 3 wherein the recess is back filled with a visible light transparent material.

5. The optical clock distribution network described in claim 1 wherein the first semiconductor comprises silicon.

6. A method for optically clocking an integrated circuit in a semiconductor having at least front and back sides, the method comprising the steps of:

receiving master laser pulses having a master clock frequency through the back side of the semiconductor into a first photo detector disposed in the semiconductor;

converting a current generated in the first photo detector in response to the master laser pulses into a clock signal; and

clocking a first area of the integrated circuit disposed in the semiconductor.

7. The method described in claim 6 including the additional step of buffering the clock signal after the step of converting the current generated in the first photo detector in the clock signal.

8. The method described in claim 6 including the additional step of:

splitting the master laser pulses into first and second split laser pulses;

wherein the step of receiving master laser pulses having the master clock frequency through the back side of the semiconductor includes the step of receiving the first and second split laser pulses into the first photo detector and a second photo detector respectively.

9. The method described in claim 8 wherein the first and second photo detectors are disposed in the semiconductor, the second split laser pulses being focused through the back side of the semiconductor.

10. The method described in claim 8 wherein the second photo detector is disposed in a second semiconductor having at least front and back sides, the second split laser pulses being received through the back side of the second semiconductor.

11. The method described in claim 10 including the additional steps of:

converting a current generated in the second photo detector in response to the second split laser pulses into the clock signal; and

clocking a second area of an integrated circuit disposed in the second semiconductor.

12. The method described in claim 6 including the step of thinning a portion of semiconductor proximate to the first photo detector and so as to reduce attenuation of the master laser pulses through the back side of the semiconductor into the first photo detector.

13. An optical clock distribution network, comprising:

a first photo detector disposed in a first semiconductor having at least front and back sides;

a mode locked laser configured to emit master laser pulses at a master clock frequency through the back side of the first semiconductor into the first photo detector; and

a first current to voltage converter coupled to the first photo detector, the first current to voltage converter generating a first clock signal configured to clock a first area of an integrated circuit disposed in the first semiconductor.

14. The optical clock distribution network described in claim 13 further comprising a first buffer coupled between the first current to voltage converter and the first area of the integrated circuit.

15. An optical clock distribution network, comprising:

a first photo detector disposed in a first semiconductor having at least front and back sides;

a second photo detector disposed in the first semiconductor;

a laser configured to emit master laser pulses at a master clock frequency through the back side of the first semiconductor into the first and second photo detectors;

a first current to voltage converter coupled to the first photo detector, the first current to voltage converter generating a first clock signal configured to clock a first area of an integrated circuit disposed in the first semiconductor;

a second current to voltage converter coupled to the second photo detector, the second current to voltage converter generating a second clock signal configured to clock a second area of the integrated circuit in the first semiconductor, the first and second clock signals having the master clock frequency; and

an optics element coupled between the laser and the first and second photo detectors, the optics element configured to split the master laser pulses into first and second split laser pulses focused through the back side of the first semiconductor into the first and second photo detectors respectively.

16. An optical clock distribution network, comprising:

a first photo detector disposed in a first semiconductor having at least front and back sides;

a second photo detector disposed in a second semiconductor having at least front and back sides;

a laser configured to emit master laser pulses at a master clock frequency through the back side of the first semiconductor into the first photo detector and through the back side of the second semiconductor into the second photo detector;

a first current to voltage converter coupled to the first photo detector, the first current to voltage converter generating a first clock signal configured to clock a first area of an integrated circuit disposed in the first semiconductor;

a second current to voltage converter coupled to the second photo detector, the second current to voltage converter generating a second clock signal configured to clock a second area of an integrated circuit in the second semiconductor, the first and second clock signals having the master clock frequency; and

an optics element coupled between the laser and the first and second photo detectors, the optics element configured to split the master laser pulses into first and second split laser pulses, the first split laser pulses focused through the back side of the first semiconductor into the first photo detector, the second split laser pulses focused through the back side of the second semiconductor into the second photo detector.