Processing system with memory arbitrating between memory access requests in a set top box

• US 5,889,949 A
• Filed: 10/11/1996
• Issued: 03/30/1999
• Est. Priority Date: 10/11/1996
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: C-Cube Corporation (Broadcom, Inc.)
• Inventors: Charles, Gordon A.
• Primary Examiner(s): RAMIREZ, ELLIS B
• Application Number:
  US08/731,343
• Time in Patent Office: 900 Days
• Field of Search: 395/800.42, 395/728, 395/732, 395/200.44, 395/200.77, 711/111, 711/112, 711/113, 711/114, 711/147, 711/148, 711/151, 711/158
• US Class Current: 709/214
• CPC Class Codes: G09G 2340/02 Handling of images in compressed format, e.g. JPEG, MPEG
• CPC Class Codes: G09G 2340/0407 Resolution change, inclusive of the use of different resolutions for different screen areas
• CPC Class Codes: G09G 2340/0442 Handling or displaying different aspect ratios, or changing the aspect ratio
• CPC Class Codes: G09G 2340/0464 Positioning
• CPC Class Codes: G09G 2340/10 Mixing of images, i.e. displayed pixel being the result of an operation, e.g. adding, on the corresponding input pixels
• CPC Class Codes: G09G 2360/02 Graphics controller able to handle multiple formats, e.g. input or output formats
• CPC Class Codes: G09G 5/06 using colour palettes, e.g. look-up tables
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory
• CPC Class Codes: H04N 11/20 Conversion of the manner in which the individual colour picture signal components are combined, e.g. conversion of colour television standards
• CPC Class Codes: H04N 21/40 Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
• CPC Class Codes: H04N 9/64 Circuits for processing colour signals H04N9/77 takes precedence; camera processing pipelines for processing colour signals H04N23/84

Abstract

A method and apparatus for providing memory arbitration which allows multiple hardware functions implemented in a single ASIC to utilize a single shared memory unit or multiple shared memory units. The memory arbitration technique establishes a priority among multiple memory access requesters and is particularly well-suited for use in a set top box processing system. A plurality of memory access requests are received from a plurality of processing elements in a set top box processing system. The processing elements include a transport stream demultiplexer, a host central processing unit and a graphics processor. The processing elements are permitted to access a shared memory in accordance with an established priority. The established priority assigns a higher priority to the graphics processor than to the host central processing unit, and may be in the order of graphics processor, transport stream demultiplexer, and central processing unit.

Claims

1. A method of arbitrating between a plurality of memory access requests from a plurality of processing elements in a set top box processing system, the processing elements including a transport stream demultiplexer, a host central processing unit and a graphics processor, the method including the steps of:

establishing a set of priorities for said processing elements, wherein said priorities are ranked according to the bandwidth and latency requirements of said processing elements, such that the higher bandwidth and lower latency elements receive the higher priority,

receiving the memory access requests from the processing elements; and

permitting the processing elements to access a shared memory in accordance with said established set of priorities, wherein said established set of priorities assigns a higher priority to the graphics processor than to the host central processing unit.

2. The method of claim 1 wherein the step of permitting the processing elements to access a shared memory in accordance with said established set of priorities further includes the step of permitting the processing elements to access a single shared memory device in accordance with said set of priorities.

3. The method of claim 1 wherein the step of permitting the processing elements to access a shared memory in accordance with said established set of priorities further includes the step of permitting the processing elements to access multiple shared memory devices in accordance with said set of priorities.

4. The method of claim 1 wherein said established set of priorities is in the order of graphics processor, transport stream demultiplexer, and central processing unit.

5. The method of claim 1 wherein the plurality of processing elements further includes an asynchronous transfer mode processing element, and said established set of priorities assigns the lowest priority to the memory access requests of the asynchronous transfer mode processing element.

6. An apparatus for arbitrating between a plurality of memory access requests in a set top box processing system, the apparatus comprising:

a memory shared by a plurality of processing elements in the set top box processing system, the processing elements including a transport demultiplexer, a host central processing unit and a graphics processor, wherein the processing elements generate the memory access requests in attempts to access the memory; and

a memory controller coupled to the memory and operative to receive the memory access requests from the processing elements, and to permit the processing elements to access the shared memory in accordance with an established set of priorities,

wherein said priorities are ranked according to bandwidth and latency requirements of said processing elements, such that the higher bandwidth and lower latency elements receive the higher priority, and

wherein said established set of priorities assigns a higher priority to the graphics processor than to the host central processing unit.

7. The apparatus of claim 6 wherein the memory shared by the plurality of processing elements is a single shared memory device.

8. The apparatus of claim 6 wherein the memory shared by the plurality of processing elements comprises multiple shared memory devices.

9. The apparatus of claim 6 wherein said established set of priorities is in the order of graphics processor, transport stream demultiplexer, and central processing unit.

10. The apparatus of claim 6 wherein the plurality of processing elements further includes an asynchronous transfer mode processing element, and said established set of priorities assigns the lowest priority to the memory access requests of the asynchronous transfer mode processing element.