Data processor having bus controller for controlling a plurality of buses independently of each other

• US 5,889,966 A
• Filed: 07/12/1996
• Issued: 03/30/1999
• Est. Priority Date: 07/13/1995
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Corporation
• Inventors: Sonobe, Satoru
• Primary Examiner(s): An, Meng-Ai T.
• Assistant Examiner(s): PHAN, RAYMOND NGAN
• Application Number:
  US08/679,128
• Time in Patent Office: 991 Days
• Field of Search: 395/306, 395/308, 395/309, 395/311, 395/281, 395/282, 395/284, 395/285, 395/287, 395/290, 395/391, 395/582, 395/840, 395/841, 395/847, 395/845, 395/856, 395/584, 395/586 , 395/520, 711/115, 711/147, 711/150
• US Class Current: 710/107
• CPC Class Codes: G06F 13/36 for access to common bus or bus system
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 9/3802 Instruction prefetching

Abstract

A data processor has a memory 100 for storing instructions being connected to a microcomputer 10 having a function of fetching an instruction from an external memory 100 via an external bus 95, a plurality of peripheral input/output circuits 40 via 49 incorporated in the microcomputer 10, and each of the peripheral input/output circuits 40 via 49 being interconnected by an incorporated peripheral bus 90, a bus controller 30 in the microcomputer 10 having both a bus state counter 31 for the external bus and a bus state counter 32 for the incorporated peripheral bus and independently controlling an external bus cycle using the external bus 95 and an incorporated peripheral bus cycle using the incorporated peripheral bus 90.

Claims

1. A data processor comprising:

a central processing unit;

first and second buses provided independently of each other;

a data path control circuit connected to said central processing unit, said first bus and said second bus;

a memory connected to said first bus and storing a string of instructions; and

a first peripheral circuit connected to said second bus and said data path control circuit;

said data path control circuit responding to a request from said central processing unit to perform a data transfer between said central processing unit and said first peripheral circuit by use of said second bus while performing an instruction prefetch operation in which an instruction stored in said memory is read out therefrom and fetched in said data path control circuit by use of said first bus,

wherein said data path control circuit includes bus controller for detecting a status of each of said first bus and said second bus by use of a first counter and a second counter, respectively, said bus controller performing said instruction prefitch operation when said first counter indicates an instruction fetch cycle and performs said data transfer when said second counter indicates an input/output cycle.

2. The data processor as claimed in claim 1, wherein said second bus, said central processing unit and said data path control circuit are formed on a single semiconductor chip, and said first bus and said memory are provided outside said single semiconductor chip.

3. A data processor comprising:

a central processing unit;

first and second buses provided independently of each other;

a data path control circuit connected to said central processing unit, said first bus and said second bus;

a memory connected to said first bus and storing a string of instructions; and

a first peripheral circuit connected to said second bus and said data path control circuit;

said data path control circuit responding to a request from said central processing unit to perform a data transfer between said central processing unit and said first peripheral circuit by use of said second bus while performing an instruction prefetch operation in which an instruction stored in said memory is read out therefrom and fetched in said data path control circuit by use of said first bus,

wherein said data path control circuit comprises;

a prefetch pointer for storing a fetch address for fetching data from said memory;

a first latch for storing an address output from said central processing unit;

a first selector for selecting one from among an address output from said first latch, an address output from said prefetch pointer, and write data output from said central processing unit;

an incrementer for incrementing an address output from said first selector and outputting the incremented address to said prefetch pointer;

a second latch for storing an address and write data which are output from said first selector and outputting them to said first bus;

a third latch for storing read data read out from said memory via said first bus;

a second selector for selecting either said read data output from said third latch or said read data from said first circuit;

a fourth latch for storing data output from said second selector and outputting said data to said central processing unit;

a third selector for selecting either an address output from said first latch or write data output from said central processing unit; and

a fifth latch for storing an address and write data output from said third selector and outputting them to said second bus;

said first selector selecting said prefetch pointer for making said fetch address and said third selector selecting said address and data for said first peripheral circuit in parallel when both said fetching cycle and said input/output cycle are requested.

4. A data processor including an incorporated microcomputer which performs an input/output operation via an incorporated peripheral bus in a incorporated peripheral bus cycle, while a central processing unit is fetching an instruction from said external memory via an external bus in a fetch cycle, comprising:

first data path means for receiving an address and data from said central processing unit, and for outputting an address and write data from said central processing unit to said external memory when said fetch cycle is requested;

second data path means provided independently of said first data path means for receiving said address and data from said central processing unit and for outputting said address and data to said input/output circuit when said incorporated peripheral bus cycle is requested; and

a bus controller which has an external bus state counter for counting the number of states of said fetch cycle and an incorporated peripheral bus state counter for counting the number of states of said incorporated peripheral bus cycle, and said bus controller which starts in parallel both an instruction fetch cycle of said external memory based on a result of a count of said external bus state counter and a data access cycle of said input/output operation based on a result of a count of said incorporated peripheral bus state counter,

wherein said first data path means includes;

a prefetch pointer for storing a fetch address for fetching data from said external memory;

a first latch for storing an address output from said central processing unit;

a first selector for selecting one from among an address output from said first latch, an address output from said prefetch pointer, and write data output from said central processing unit;

an incrementer for incrementing an address output from said first selector and outputting the incremented address to said prefetch pointer; and

a second latch for storing an address and write data that are output from said first selector and outputting them to said external bus.

5. The data processor as claimed in claim 4, wherein said second data path means includes

second selector for selecting either said address output form said first latch or said write data output from said central processing unit;

and

a third latch for storing said address and write data output from said second selector and outputting them to said incorporated peripheral bus;

said first selector selecting said prephetch pointer and said second selector selecting said address and write data for peripheral input/output circuit in parallel when both said fetch cycle and said incorporated peripheral bus cycle are requested.

6. A data processor including an incorporated microcomputer which performs an input/output operation via an incorporated peripheral bus in a incorporated peripheral bus cycle, while a central processing unit is fetching an instruction from said external memory via an external bus in a fetch cycle, comprising:

first data path means for receiving an address and data from said central processing unit, and for outputting an address and write data from said central processing unit to said external memory when said fetch cycle is requested;

second data path means provided independently of said first data path means for receiving said address and data from said central processing unit and for outputting said address and data to said input/output circuit when said incorporated peripheral bus cycle is requested; and

a bus controller which has an external bus state counter for counting the number of states of said fetch cycle and an incorporated peripheral bus state counter for counting the number of states of said incorporated peripheral bus cycle, and said bus controller which starts in parallel both an instruction fetch cycle of said external memory based on a result of a count of said external bus state counter and a data access cycle of said input/output operation based on a result of a count of said incorporated peripheral bus state counter,

wherein said incorporated peripheral bus, said central processing unit, said first data path means, said second data path means, said bus controller and said input/output circuit are formed in a same chip, and said external bus and said external memory formed outside said chip.