Cooperation of global and local register allocators for better handling of procedures
First Claim
Patent Images
1. A computer-implemented method of mapping an arbitrary number of symbolic registers onto a finite set of hardware registers in a computational device, comprising the steps of:
- partitioning said symbolic registers into first and second portions;
assigning said first portion of said symbolic registers to said hardware registers using a first register allocator, wherein said first register allocator is a local register allocator having a first allocation operation; and
assigning said second portion of said symbolic registers to said hardware registers using a second register allocator, wherein said second register allocator is a global register allocator having a second allocation operation, and wherein said first allocation operation is faster than said second allocation operation.
2 Assignments
0 Petitions
Accused Products
Abstract
A method and device for optimizing a compiler involves cooperation between the global and local register allocators in assigning symbolic registers to hardware registers. A large procedure may have many associated symbolic registers; the invention involves partitioning the symbolic registers into at least two portions, and allowing the global register allocator to assign one portion and the local register allocator to assign another portion. The registers may be partitioned based on different criteria, such as local vs. global registers, or spill costs, or shallow vs. nested regions.
-
Citations
13 Claims
-
1. A computer-implemented method of mapping an arbitrary number of symbolic registers onto a finite set of hardware registers in a computational device, comprising the steps of:
-
partitioning said symbolic registers into first and second portions; assigning said first portion of said symbolic registers to said hardware registers using a first register allocator, wherein said first register allocator is a local register allocator having a first allocation operation; and assigning said second portion of said symbolic registers to said hardware registers using a second register allocator, wherein said second register allocator is a global register allocator having a second allocation operation, and wherein said first allocation operation is faster than said second allocation operation. - View Dependent Claims (2, 3, 4, 5, 6, 7)
-
-
8. A computer-implemented method of compiling computer code containing at least one procedure, to create object code which is to be loaded into a computer having a plurality of hardware registers, by optimizing compile time and efficiency of the object code, comprising the steps of:
-
creating a plurality of symbolic registers based on said procedure; partitioning said symbolic registers into first and second portions; assigning said first portion of said symbolic registers to said plurality of hardware registers using a local register allocator having a first allocation operation with a first efficiency level of code creation; and assigning said second portion of said symbolic registers to said plurality of hardware registers using a global register allocator having a second allocation operation with a second efficiency level of code creation, wherein the first allocation operation is faster than the second allocation operation and the first efficiency level of code creation is less efficient than the second efficiency level of code creation. - View Dependent Claims (9, 10, 11, 12, 13)
-
Specification
-
- Resources
Litigation Campaign Assessment
Thank you for your request. You will receive a custom alert email when the Litigation Campaign Assessment is available.
×
-
Current AssigneeInternational Business Machines Corporation
-
Original AssigneeInternational Business Machines Corporation
-
InventorsAizikowitz, Nava E., Edelstein, Orit, Bar-Haim, Roy N., Roediger, Robert Ralph, Prosser, Edward Curtis
-
Primary Examiner(s)Trammell, James P.
-
Assistant Examiner(s)Nguyen, Cuong H.
-
Application NumberUS08/760,176Time in Patent Office846 DaysField of Search711/202-203, 711/209, 711/109, 395/708, 395/707, 395/709, 395/651, 395/705, 395/393-394, 395/591, 395/674US Class Current717/154CPC Class CodesG06F 8/441 Register allocation; Assign...
