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Interrupts between asynchronously operating CPUs in fault tolerant computer system

  • US 5,890,003 A
  • Filed: 09/07/1993
  • Issued: 03/30/1999
  • Est. Priority Date: 12/09/1988
  • Status: Expired due to Term
First Claim
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1. A multiple CPU system, comprising:

  • a) a plurality of CPUs concurrently executing a same instruction stream, the CPUs being the only CPUs in the multiple CPU system and wherein all of the CPUs in the multiple CPU system are clocked independently of one another to provide separate machine clock cycles for each CPU, so that said instruction stream is executed asynchronously over plural instructions and any of said CPUs may be leading other of said CPUs, said machine clock cycles including execution cycles where an instruction of said instruction stream is executed and stall cycles where an instruction of said instruction stream is not executed, each CPU having a memory request input/output port;

    b) a common memory coupled to the input/output ports of said CPUs, the common memory implementing a memory request only after receiving identical requests from all of said CPUs, the memory sending an acknowledge signal to the CPUs when implementing a memory request, each of the CPUs executing stall cycles while awaiting implementation of a memory request by the common memory as signaled by said acknowledge signal;

    c) each of the CPUs having a counter to count machine clock cycles corresponding to execution cycles but which is inhibited from counting machine clock cycles corresponding to stall cycles; and

    d) all of said CPUs in the system having an interrupt circuit responsive to an external interrupt request occurring at any time unsynchronized with said execution of said instruction stream, said interrupt circuit being coupled to said counters in said CPUs and responsive to a selected count in each of said counters for separately interrupting each CPU at an identical instruction execution cycle, any one of the CPUs which may be leading being interrupted first while other of said CPUs continue to execute instructions so that if said CPUs are executing different instructions in said stream then said CPUs may be interrupted at different instants in real time.

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