Low power, low interconnect complexity microprocessor and memory interface
First Claim
1. A method for reducing the power consumption of an electronic system having a first device and a second device that are coupled together through a bidirectional bus, comprising the steps of:
- during a first part of a bus cycle, applying an address over the bus from the first device to the second device;
during a second part of the bus cycle, transferring data to or from the first device over at least a portion of the bidirectional bus; and
prior to the step of transferring, selectively inverting or not inverting the data, regardless of whether there is to be a chance in direction of data to be transferred over the bidirectional bus, so as to minimize a number of bus signal lines that are required to change state between the first part and the second part of the bus cycle, thereby reducing power consumption by at least reducing an amount of bus capacitance that is required to be charged or discharged in order to transfer the data during the second part of the bus cycle.
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Accused Products
Abstract
A method is disclosed for reducing the power consumption of an electronic system, such as a wireless or cellular telephone, that has a memory and a device for accessing the memory. The method includes the steps of (a)during a first part of a memory access cycle, applying an address over a bus; (b) during a second part of the memory access cycle, transferring data to or from the memory over at least a portion of the bus; and (c) prior to the step of transferring, selectively inverting or not inverting the data so as to minimize a number of bus signal lines that are required to change state between the first part and the second part of the memory access cycle. In a preferred embodiment of the invention the bus is a multiplexed address/data bus. The method also generates a control signal that is transmitted to the bus for informing a receiving device that the data (or address) being transferred over the multiplexed address/data bus should be inverted before use. Also disclosed is a memory that operates in a burst mode by incrementing or decrementing memory addresses using a clock signal, and that operates with the power saving circuitry to selectively invert or not invert burst mode data read from or written to the memory.
80 Citations
29 Claims
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1. A method for reducing the power consumption of an electronic system having a first device and a second device that are coupled together through a bidirectional bus, comprising the steps of:
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during a first part of a bus cycle, applying an address over the bus from the first device to the second device; during a second part of the bus cycle, transferring data to or from the first device over at least a portion of the bidirectional bus; and prior to the step of transferring, selectively inverting or not inverting the data, regardless of whether there is to be a chance in direction of data to be transferred over the bidirectional bus, so as to minimize a number of bus signal lines that are required to change state between the first part and the second part of the bus cycle, thereby reducing power consumption by at least reducing an amount of bus capacitance that is required to be charged or discharged in order to transfer the data during the second part of the bus cycle. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A wireless telephone, comprising:
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a microprocessor; a memory; a bus coupling said microprocessor to said memory, said bus comprising a multiplexed address/data bidirectional bus portion that transfers an address during a first part of a memory access cycle and data during a second part of the memory access cycle; and power saving circuitry coupled to said bus, said power saving circuitry being operative during the second part of a memory access cycle for selectively inverting or not inverting the data, regardless of whether there is to be a change in direction of data to be transferred over the bidirectional bus portion, so as to minimize a number of multiplexed address/data bus signal lines that are required to change state between the first part and the second part of the memory access cycle, thereby reducing power consumption by at least reducing an amount of bus capacitance that is required to be charged or discharged in order to transfer the data during the second part of the memory access cycle. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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- 18. An electronic device, comprising a plurality of terminals for coupling the electronic device to a bidirectional bus that is external to said electronic device, and also comprising a further terminal for coupling to a bus control signal that indicates, during operation, whether information currently being transferred over said bidirectional bus has been inverted, regardless of whether there was a change in direction of data that was last transferred over the bidirectional bus, in order to minimize a number of bus signal lines that are required to change state between information that was last transferred and the information that is currently being transferred, the inversion of the information being selectively accomplished so as to reduce power consumption by at least reducing an amount of bus capacitance that is required to be charged or discharged in order to transfer the information.
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25. A method for reducing the power consumption of an electronic system having a memory array and a device that are coupled together through a bus, comprising the steps of:
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during a first part of a bus cycle, applying an address over the bus from the device to the memory array; in response to the applied address, reading out a plurality of memory array locations in parallel and storing the data output from the memory array locations in a plurality of latches; during a second part of the bus cycle, transferring data in turn from each of the latches over at least a portion of the bus; and prior to at least some of the steps of transferring, selectively inverting or not inverting the data so as to minimize a number of bus signal lines that are required to change state, thereby reducing power consumption by at least reducing an amount of bus capacitance that is required to be charged or discharged in order to transfer the data during the second part of the memory access cycle, wherein the step of selectively inverting includes a step of comparing data to be output from one of the latches to data stored in another one of the latches, and wherein the step of selectively inverting is performed based on the result of the comparison. - View Dependent Claims (26, 27, 28, 29)
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Specification