Method of fabricating EEPROM using oblique implantation

• US 5,891,774 A
• Filed: 09/03/1996
• Issued: 04/06/1999
• Est. Priority Date: 11/17/1995
• Status: Expired due to Term

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Tanaka, Masaaki, Ueda, Naoki, Tanaka, Kenichi
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US08/707,076
• Time in Patent Office: 945 Days
• Field of Search: 438/257, 438/264, 438/286, 438/302, 438/525, 438/545
• US Class Current: 438/264
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor memory device is provided which comprises: a plurality of memory cell transistors each having a tunnel oxide film formed on a semiconductor substrate of a first conductivity type, a floating gate formed on the tunnel oxide film, a control gate overlaid on the floating gate with intervention of an insulating film, source/drain regions of a second conductivity type formed in the semiconductor substrate, and a high-concentration impurity layer of the first conductivity type formed in a portion adjacent to the drain region below the floating gate by oblique ion implantation employing an implantation angle θ with respect to a normal line to the semiconductor substrate; the plurality of memory cell transistors each sharing a source region with a memory cell transistor disposed adjacent thereto on one side thereof and a drain region with a memory cell transistor disposed adjacent thereto on the other side thereof; the implantation angle θ being defined by the following expression:

0<tan^-1 (Ld/Hg)<θ<tan^-1 (Ls/Hg)<π/2

wherein Ls is a distance between gates of the adjacent transistors sharing the source region, Ld is a distance between gates of the adjacent transistors sharing the drain region, and Hg is a total height of the floating gate, the insulating film and the control gate on the tunnel oxide film.

Claims

1. A process for fabricating a semiconductor memory device comprising the steps of:

(i) defining a device formation region comprising a plurity of memory cell transistor on a semiconductor substrate of a first conductivity type, and forming a tunnel oxide film, a floating gate, an insulating film and a control gate in this order;

wherein the plurality of memory cell transistors share a source region with a memory cell transistor disposed adjacent thereto on one side thereof and a drain region with a memory cell transistor disposed adjacent thereto on the other side thereof;

(ii) performing a first oblique ion implantation process employing an ion implantation angle of θ

with respect to a normal line to the semiconductor substrate and a second oblique ion implantation employing an ion implantation angle of -θ

°

, using the floating gate and the control gate as a mask, to form a high-concentration impurity layer of the first conductivity type in a portion adjacent to a drain formation region below the floating gate, the angle θ

being defined by the following expression;

0<

tan^-1 (Ld/Hg)<

θ

<

tan^-1 (Ls/Hg)<

π

/2

wherein Ls is a distance between gates of the adjacent transistors sharing the source region, Ld is a distance between gates of the adjacent transistors sharing the drain region, and Hg is a total height of at least the floating gate, the insulating film and the control gate on the tunnel oxide film; and

iii) implanting ions into the semiconductor substrate from a direction generally normal to the semiconductor substrate by using the floating gate and the control gate as a mask to form source/drain regions of a second conductivity type.

2. A process as set forth in claim 1, wherein an impurity of the first conductivity type is implanted into the entire device formation region to optimize an impurity concentration in a portion adjacent to the source region below the floating gate in the semiconductor substrate in the step (i).

3. A process as set forth in claim 1, wherein a resist pattern having an opening only on a source formation region is formed before the formation of the source/drain regions, and ions are implanted from a direction normal to the semiconductor substrate by using the resist pattern as a mask to form a low-concentration impurity layer of the second conductivity type in a peripheral portion of the source formation region or in a portion adjacent to the source formation region below the floating gate in the step (iii).

4. A process as set forth in claim 1, wherein an insulating film spacer is formed on the control gate in the step (i), and the height Hg in the step (ii) is a total height of the floating gate, the insulating film, the control gate and the insulating spacer.