SOI-type semiconductor device with variable threshold voltages

• US 5,892,260 A
• Filed: 01/26/1996
• Issued: 04/06/1999
• Est. Priority Date: 01/27/1995
• Status: Expired due to Fees

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Okumura, Koichiro, Kurosawa, Susumu
• Primary Examiner(s): CRANE, SARA W
• Application Number:
  US08/592,635
• Time in Patent Office: 1,166 Days
• Field of Search: 257/347, 257/351, 257/399, 257/372, 257/901, 257/906, 257/57, 257/316, 257/510, 327/536, 327/543, 327/535, 327/537, 365/226
• US Class Current: 257/347
• CPC Class Codes: G05F 3/242 with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
• CPC Class Codes: H01L 27/0218 of field effect structures
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/78615 with a body contact
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET
• CPC Class Codes: Y10S 257/901 MOSFET substrate bias

Abstract

In an SOI-type semiconductor device, a power supply voltage is applied to back gates of P-channel MOS transistors in a standby mode, and a voltage lower than the power supply voltage is applied to the back gates of the P-channel MOS transistors in an active mode. A ground voltage is applied to back gates of N-channel MOS transistors in the standby mode, and a voltage higher than the ground voltage is applied to the back gates of the N-channel MOS transistors in an active mode.

Claims

1. A semiconductor device comprising:

a first power supply terminal for supplying a first power supply voltage;

a second power supply terminal for supplying a second power supply voltage lower than said first power supply voltage;

a semiconductor substrate;

a first insulating layer formed on said semiconductor substrate;

a semiconductor layer formed on said first insulating layer;

a plurality of P-channel MOS transistors formed in said semiconductor layer, each of said plurality of P-channel MOS transistors having a corresponding N-type back gate region, a P-type source region and a P-type drain region in direct contact with said first insulating layer, and each of said plurality of P-channel MOS transistors having a PN junction, each PN junction having an unbiased forward voltage barrier of a common PN junction;

a plurality of N-channel MOS transistors formed in said semiconductor layer, each of said plurality of N-channel MOS transistors having a corresponding P-type back gate region, an N-ype source region and an N-type drain region in direct contact with said first insulating layer, and each of said plurality of N-channel MOS transistors having a PN junction having said unbiased forward voltage barrier;

at least one bias voltage generating circuit, electrically connected to said first and second power supply terminals, said P-channel MOS transistors and said N-channel MOS transistors, for applying said first power supply voltage to the back gates of said P-channel MOS transistors and said second power supply voltage to the back gates of said N-channel MOS transistors when said device is in a standby mode and for applying a first voltage to the back gates of said P-channel MOS transistors and a second voltage to the back gates of said N-channel MOS transistors when said device is in an active mode,

said first voltage being a positive voltage and being lower than said first power supply voltage and higher than said first power supply voltage minus said unbiased forward voltage barrier of the PN junctions of said P-channel MOS transistors,

said second voltage being higher than said second power supply voltage and lower with respect to positive than said unbiased forward voltage barrier of the PN junctions of said N-channel MOS transistors.

2. A device as set forth in claim 1, further comprising a second insulating layer for electrically isolating said P-channel MOS transistors and said N-channel MOS transistors from each other.

3. A device as set forth in claim 1, wherein said semiconductor layer is approximately 30 to 200 nm thick.

4. A device as set forth in claim 1, wherein said P-channel MOS transistors and said N-channel MOS transistors are grouped into a plurality of blocks,

and wherein said bias voltage generating circuit connects to one of said blocks, so that said block is operated individually in said standby mode and in said active mode.

5. A device as set forth in claim 1, wherein said bias voltage generating circuit comprises:

a first switching element connected between said first power supply terminal and the back gates of said P-channel MOS transistors, said first switching element being turned ON in said standby mode and being turned OFF in said active mode;

a first diode means formed by a P-channel MOS transistor and connected between said first power supply terminal and the back gates of said P-channel MOS transistors, said first diode means having a first threshold voltage;

a second diode means formed by a PNP-type transistor having PN junctions having said unbiased forward voltage barrier, and connected between said first power supply terminal and the back gates of said P-channel MOS transistors, an absolute value of said first threshold voltage of said first diode means being smaller than said unbiased forward voltage barrier of the PN junctions of said second diode means;

a second switching element connected between the back gates of P-channel MOS transistors and said second power supply terminal, said second switching element being turned OFF in said standby mode and being turned ON in said active mode;

a third switching element connected between the back gates of said N-channel MOS transistors and said second power supply terminal, said third switching element being turned ON in said standby mode and being turned OFF in said active mode;

a third diode means formed by an N-channel MOS transistor and connected between the back gates of said N-channel MOS transistors and said second power supply terminal, said third diode means having a second threshold voltage;

a fourth diode means formed by an NPN-type transistor having PN junctions having said unbiased forward voltage barrier, and connected between the back gates of said N-channel MOS transistors and said second power supply terminal, an absolute value of said second threshold voltage of said third diode means being smaller than said unbiased forward voltage barrier of said fourth diode means;

a fourth switching element connected between said first power supply terminal and the back gates of said N-channel MOS transistors, said fourth switching element being turned OFF in said standby mode and being turned ON in said active mode.

6. A device as set forth in claim 5, wherein:

said first switching element comprises a P-channel MOS transistors which turns ON in response to an active mode signal generated from said device,

said second switching element comprises an N-channel MOS transistor which turns ON in response to said active mode signal,

said third switching element comprises an N-channel MOS transistor which turns ON in response to an inverted signal of said active mode signal,

said fourth switching element comprises a P-channel MOS transistor which turns ON in response to the inverted signal of said active mode signal.

7. A device as set forth in claim 5, further comprising:

a first resistor connected in series to said second switching element between said first power supply terminal and the back gates of said P-channel MOS transistors; and

a second resistor connected in series to said fourth switching element between said first power supply terminal and the back gates of said N-channel MOS transistors.

8. A device as set forth in claim 5, further comprising;

a fifth switching element connected between the back gates of said P-channel MOS transistors and said second power supply terminal;

a sixth switching element connected between said first power supply terminal and the back gates of said N-channel MOS transistors; and

a first one-shot pulse generating circuit for generating a first pulse signal and a second pulse signal in response to a transition from said standby mode to said active mode, said first pulse signal being transmitted to said fifth switching element to turn ON said fifth switching element, said second pulse signal being transmitted to said sixth switching element to turn ON said sixth switching element.

9. A device as set forth in claim 8, wherein said fifth switching element comprises an N-channel MOS transistor, and

said sixth switching element comprises a P-channel MOS transistor.

10. A device as set forth in claim 8, further comprising:

a seventh switching element connected between the back gates of said P-channel MOS transistors and said second power supply terminal;

an eighth switching element connected between said first power supply terminal and the back gates of said N-channel MOS transistors; and

a second one-shot pulse generating circuit for generating a third pulse signal having a smaller pulse width than said first pulse signal and a fourth pulse signal having a smaller pulse width than said second pulse signal in response to a transition from said standby mode to said active mode, said third pulse signal being transmitted to said seventh switching element to turn ON said seventh switching element, said fourth pulse signal being transmitted to said eighth switching element to turn ON said eighth switching element.

11. A device as set forth in claim 10, wherein said seventh switching element comprises an N-channel MOS transistor, and

said eighth switching element comprises a P-channel MOS transistor.

12. A device as set forth in claim 1, wherein said bias voltage generating circuit comprises:

a first switching element connected between said first power supply terminal and the back gates of said P-channel MOS transistors, said first switching element being turned ON in said standby mode and being turned OFF in said active mode;

a first diode means formed by a P-channel hybrid mode device and connected between said first power supply terminal and the back gates of said P-channel MOS transistors;

a second switching element connected between the back gates of said N-channel MOS transistors and said second power supply terminal, said third switching element being turned ON in said standby mode and being turned OFF in said active mode;

a third diode means formed by an N-channel hybrid mode device and connected between the back gates of said N-channel MOS transistors and said second power supply terminal; and

a fourth switching element connected between said first power supply terminal and the back gates of said N-channel MOS transistors, said fourth switching element being turned OFF in said standby mode and being turned ON in said active mode.

13. A device as set forth in claim 12, wherein:

said first switching element comprises a P-channel MOS transistor which turns ON in response to an active mode signal generated from said device,

said second switching element comprises an N-channel transistor which turns ON in response to said active mode signal,

said third switching element comprises an N-channel MOS transistor which turns ON in response to an inverted signal of said active mode signal, and

said fourth switching element comprises a P-channel MOS transistor which turns ON in response to the inverted signal of said active mode signal.

14. A device as set forth in claim 12, further comprising:

a first resistor connected in series to said second switching element between said first power supply terminal and the back gates of said P-channel MOS transistors; and

a second resistor connected in series to said fourth switching element between said first power supply terminal and the back gates of said N-channel MOS transistors.

15. A device as set forth in claim 12, further comprising:

a fifth switching element connected between the back gates of said P-channel MOS transistors and said second power supply terminal;

a sixth switching element connected between said first power supply terminal and the back gates of said N-channel MOS transistors; and

a first one-shot pulse generating circuit for generating a first pulse signal and a second pulse signal in response to a transition from said standby mode to said active mode, said first pulse signal being transmitted to said fifth switching element to turn ON said fifth switching element, said second pulse signal being transmitted to said sixth switching element to turn ON said sixth switching element.

16. A device as set forth in claim 15, wherein said fifth switching element comprises an N-channel MOS transistor, and

said sixth switching element comprises a P-channel MOS transistor.

17. A device as set forth in claim 15, further comprising:

a seventh switching element connected between the back gates of said P-channel MOS transistors and said second power supply terminal;

an eighth switching element connected between said first power supply terminal and the back gates of said N-channel MOS transistors; and

a second one-shot pulse generating circuit for generating a third pulse signal having a smaller pulse width than said first pulse signal and a fourth pulse signal having a smaller pulse width than said second pulse signal in response to a transition from said standby mode to said active mode, said third pulse signal being transmitted to said seventh switching element to turn ON said seventh switching element, said fourth pulse signal being transmitted to said eighth switching element to turn ON said eighth switching element.

18. A device as set forth in claim 17, wherein said seventh switching element comprises an N-channel MOS transistor, and

said eighth switching element comprises a P-channel MOS transistor.