Bare chip mounting structure and manufacturing method therefor

• US 5,892,289 A
• Filed: 04/22/1997
• Issued: 04/06/1999
• Est. Priority Date: 04/22/1996
• Status: Expired due to Fees

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Tokuno, Kenichi
• Primary Examiner(s): Saadat, Mahshid
• Assistant Examiner(s): CLARK, SHEILA V
• Application Number:
  US08/837,801
• Time in Patent Office: 714 Days
• Field of Search: 257/789, 257/787, 257/782, 257/783, 257/778
• US Class Current: 257/783
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/29111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/83102 using surface energy, e.g. capillary forces
• CPC Class Codes: H01L 2224/92125 the second connecting process involving a layer connector
• CPC Class Codes: H01L 24/28 Structure, shape, material or disposition of the layer connectors prior to the connecting process
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/15151 : the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/1579 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy

Abstract

A mounting structure is provided which improves the reliability of the connection between the bumps at the four corners of a flip-chip mounted semiconductor chip which is subject to stress concentrations caused by board warping or a difference in thermal coefficient of expansion when subjecting the mounted chip to thermal cycling tests. In this structure, a sealing resin is caused to flow into a space between the semiconductor chip and the board at the four corners of the semiconductor chip, thereby forming large resin fillets at the four corners, these fillets relieving the above-noted stress at the bump connection parts of the four corners of the semiconductor chip, thereby causing an improvement in reliability of the connection. The flowing distance is shortened and simultaneous flowing resin is performed, thereby shortening the time required for sealing.

Claims

1. A manufacturing method for a bare chip mounting structure comprising applying a sealing resin to at least two corners of a semiconductor chip and causing the sealing resin to flow into a space between said semiconductor chip and a substrate, onto which said semiconductor chin is flip-chip mounted, wherein the sealing resin is potted at a place on the substrate apart from a corner of said semiconductor chip and along an extension of a diagonal line thereof, by a distance being longer than that of a radius of a potting needle but shorter than a center position of said sealing resin just potted from said needle at which a part of said sealing resin can contact to a side surface of said semiconductor chip.

2. A mounted semiconductor chip structure comprising:

a substrate;

a semiconductor chip flip-chip mounted to the semiconductor substrate;

resin disposed between the substrate and the semiconductor chip, the resin extending beyond a perimeter of the semiconductor chip to form resin fillets, wherein the fillets at two or more corners of the semiconductor chip extend farther from a nearest edge of the semiconductor chip than do the fillets at sides of the semiconductor chip.

3. The mounted semiconductor chip structure of claim 2, wherein the fillets at all corners of the semiconductor chip extend farther from a nearest edge of the semiconductor chip than do the fillets at sides of the semiconductor chip.

4. The mounted semiconductor chip structure of claim 2, wherein each of the outward extending fillets at two or more corners of the semiconductor chip has a curved outer edge.

5. The mounted semiconductor chip structure of claim 2, wherein at least one of the fillets contacts a side wall of the semiconductor chip.

6. The mounted semiconductor chip structure of claim 5, wherein the at least one fillet contacting a side wall of the semiconductor chip has an upper edge which coincides with an upper edge of the semiconductor chip.

7. The mounted semiconductor chip structure of claim 6, wherein the at least one fillet contacting a side wall of the semiconductor chip covers at least a portion of a top surface of the semiconductor chip.

16. The mounted semiconductor chip structure of claim 2, wherein the fillets at two or more corners of the semiconductor chip extend beyond an intersection point of lines representing outside edges of the fillets at adjacent sides of the semiconductor chip.

8. A method for manufacturing a mounted semiconductor chip structure, comprising the steps of:

providing a substrate;

attaching a semiconductor chip to the substrate using a flip-chip method; and

introducing sealing resin at two or more corners of the semiconductor chip and causing the sealing resin to flow into a space between the semiconductor chip and the substrate;

wherein the sealing resin is potted at points on the substrate located on respective diagonal lines extending from the corners of the semiconductor chip, the points being located a distance from a nearest corner of the semiconductor chip which is greater than a radius of a potting needle used and less than a radius of the sealing resin as initially potted.

9. The method of claim 8, wherein the sealing resin is introduced at all of the corners of the semiconductor chip.

10. The method of claim 9, wherein the sealing resin creates at least one fillet which contacts a side wall of the semiconductor chip.

11. The method of claim 10, wherein the at least one fillet contacting a side wall of the semiconductor chip has an upper edge which coincides with an upper edge of the semiconductor chip.

12. The method of claim 11, wherein the at least one fillet contacting a side wall of the semiconductor chip covers at least a portion of a top surface of the semiconductor chip.

13. The method of claim 8, wherein the sealing resin creates at least one fillet which contacts a side wall of the semiconductor chip.

14. The method of claim 13, wherein the at least one fillet contacting a side wall of the semiconductor chip has an upper edge which coincides with an upper edge of the semiconductor chip.

15. The method of claim 13, wherein the at least one fillet contacting a side wall of the semiconductor chip covers at least a portion of a top surface of the semiconductor chip.