Clock network for field programmable gate array
First Claim
1. A field programmable gate array, comprising:
- a first clock bus extending in a first dimension and having a first segment extending in the first dimension, a second segment extending in the first dimension substantially collinear with respect to the first segment, the first segment being programmably couplable to the second segment;
a first driver circuit having an input coupled to the first segment of the first clock input bus;
a second clock bus extending in the first dimension parallel to said first clock bus, the second clock bus being coupled to an output of the first driver circuit; and
a plurality third clock buses extending in a second dimension perpendicular to the first dimension, each third clock bus having a second driver circuit an input of which is coupled to the second clock bus and an output of which is coupled to the third clock bus.
2 Assignments
0 Petitions
Accused Products
Abstract
A clock network of a field programmable gate array has a first clock bus extending across the chip in a first dimension. A clock pad can be coupled to the first clock bus if the clock network is to be driven from the clock pad. An output of a selected logic cell can be coupled to the first clock bus if the clock network is to be driven from a logic cell. To increase speed of the clock network, the first clock bus is segmented (in one embodiment, collinearly extending segments can be selectively coupled together via selectively programmable antifuses) so that only a short piece of the first clock bus is used to couple either the pad or the logic cell to the clock network in high speed applications.
-
Citations
19 Claims
-
1. A field programmable gate array, comprising:
-
a first clock bus extending in a first dimension and having a first segment extending in the first dimension, a second segment extending in the first dimension substantially collinear with respect to the first segment, the first segment being programmably couplable to the second segment; a first driver circuit having an input coupled to the first segment of the first clock input bus; a second clock bus extending in the first dimension parallel to said first clock bus, the second clock bus being coupled to an output of the first driver circuit; and a plurality third clock buses extending in a second dimension perpendicular to the first dimension, each third clock bus having a second driver circuit an input of which is coupled to the second clock bus and an output of which is coupled to the third clock bus. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
-
-
14. A method, comprising:
-
coupling a pad to only one segment of a segmented first clock bus of a field programmable gate array, the segmented first clock bus having a plurality of segments which can be coupled together; and supplying a signal from the pad and onto a second clock bus via the one segment. - View Dependent Claims (15, 16)
-
-
17. A method, comprising:
-
coupling an output of a logic cell to only one segment of a segmented first clock bus of a field programmable gate array, the segmented first clock bus having a plurality of segments which can be coupled together; and supplying a signal from the logic cell and onto a second clock bus via the one segment. - View Dependent Claims (18, 19)
-
Specification