Method for shaping a pulse width and circuit therefor
First Claim
1. A semiconductor detector circuit, comprising:
- a first latch having a first input, a second input, and an output;
a second latch having a first input, a second input, and an output;
a first buffer having an input coupled to the output of the first latch and an output;
a second buffer having an input coupled to the output of the second latch and an output; and
a logic circuit having a first input coupled to the output of the first buffer, a second input coupled to the output of the first latch, a third input coupled to the output of the second buffer, and an output coupled to the second input of the first latch and to the second input of the second latch that provides a reset signal at the output of the logic circuit when signals at the first, second, and third inputs of the logic circuit transition to a first logic state.
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Abstract
A phase-frequency detector (12) is configured for operating at a high frequency. A transition of a clock signal (REF CLK) is detected by a first latch (52) and a signal UP is generated. A transition of a feedback signal (FBK) is detected by a second latch (56) and a signal DOWN is generated. An logic circuit (64) detects the signals UP and the DOWN and generates a reset signal (RESET). A pulse-width of the reset signal (RESET) is controlled and limited by the logic circuit (64) to provide a faster response time for setting the first and second latches (52 and 56) to a state that allows detection of the phase and frequency differences between the clock signal (REF CLK) and the feedback signal (FBK).
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Citations
13 Claims
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1. A semiconductor detector circuit, comprising:
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a first latch having a first input, a second input, and an output; a second latch having a first input, a second input, and an output; a first buffer having an input coupled to the output of the first latch and an output; a second buffer having an input coupled to the output of the second latch and an output; and a logic circuit having a first input coupled to the output of the first buffer, a second input coupled to the output of the first latch, a third input coupled to the output of the second buffer, and an output coupled to the second input of the first latch and to the second input of the second latch that provides a reset signal at the output of the logic circuit when signals at the first, second, and third inputs of the logic circuit transition to a first logic state. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A phase-frequency detection circuit, comprising:
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first and second memory devices; a first buffer having an input coupled to an outout of the first memory device and an output; a second buffer having an input coupled to an output of the second memory device and an output; and a logic circuit having a first input coupled to the output of the first memory device, a second input coupled to the output of the first buffer, a third input coupled to the output of the second buffer, and an output that provides a reset signal to the first and second memory devices, the reset signal being a logical AND of signals transitioning to a first logic state at the first, second, and third inputs of the logic circuit. - View Dependent Claims (8, 9)
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10. A method for shaping a pulse-width, comprising the steps of:
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detecting a transition of a first input signal by setting a first latch; causing a first signal and a first buffered signal to transition to a first logic state after setting the first latch; detecting a transition of a second input signal by setting a second latch; causing a second buffered signal to transition to the first logic state after setting the second latch; generating a pulse by detecting that the first buffered signal, the second buffered signal, and the first signal are in the first logic state; resetting the first and second latches with the pulse; and terminating the pulse upon detecting that the first signal has transitioned to a second logic state based on resetting the first latch. - View Dependent Claims (11, 12, 13)
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Specification