Current mode logic circuit, source follower circuit and flip flop circuit

• US 5,892,382 A
• Filed: 08/01/1997
• Issued: 04/06/1999
• Est. Priority Date: 03/25/1997
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Wada, Yoshiki, Ueda, Kimio, Hirano, Yuuichi
• Primary Examiner(s): TRAN, TOAN V
• Application Number:
  US08/904,940
• Time in Patent Office: 613 Days
• Field of Search: 327/199, 327/202, 327/203, 327/208, 327/108, 327/65-67, 327/77, 327/112, 327/427, 327/334
• US Class Current: 327/202
• CPC Class Codes: H03K 19/09432 with coupled sources or source coupled logic H03K19/096 takes precedence
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET
• CPC Class Codes: H03K 3/35613 the input circuit having a differential configuration
• CPC Class Codes: H03K 3/3562 of the master-slave type

Abstract

A current mode logic circuit has a first and second NMOS transistors N1 and N2, an input terminal IN connected to both gates of the first and second NMOS transistors N1 and N2 to input data, a reference voltage input terminal REF, an output terminal OUT connected to a drain of the first NMOS transistor N1, and a current power source I connected both sources of the first and second NMOS transistors N1 and N2. Body terminals of the first and second NMOS transistors N1and N2 are connected to the input terminal IN and the reference terminal REF, respectively so that the body voltage of each of the first and second NMOS transistors N1 and N2 is controlled.

Claims

1. A source follower circuit forming a current switch comprising:

a first NMOS transistor and a second NMOS transistor, a third NMOS transistor connected to a source of the first NMOS transistor,

an fourth NMOS transistor connected to a source of the second NMOS transistor; and

a current power source connected to both of the sources of the third NMOS transistor and the fourth NMOS transistor,

wherein both gates of the first NMOS transistor and the fourth NMOS transistor form a first input terminal to which a first input is provided, both gates of the second NMOS transistor and the third NMOS transistor form a second input terminal to which a second input whose level is obtained by inverting the level of the first input is provided, the source of the first NMOS transistor is connected to a drain of the third NMOS transistor and to a first output, and the source of the second NMOS transistor is connected to a drain of the fourth NMOS transistor and to a second output.

2. A source follower circuit as claimed in claim 1, wherein resistors are connected between the source of the third NMOS transistor and the current power source, and between the source of the fourth NMOS transistor and the current power source, respectively.

3. A flip flop circuit comprising:

a source follower circuit including

a first NMOS transistor and a second NMOS transistor;

a third NMOS transistor connected to a source of the first NMOS transistor

an fourth NMOS transistor connected to a source of the second NMOS transistor; and

a current power source connected to both of the sources of the third NMOS transistor and the fourth NMOS transistor

wherein both gates of the first NMOS transistor and the fourth NMOS transistor form a first input terminal to which a first input is provided, both gates of the second NMOS transistor and the third NMOS transistor form a second input terminal to which a second input whose level is obtained by inverting the level of the first input is provided, the source of the first NMOS transistor is connected to a drain of the third NMOS transistor and to a first output, and the source of the second NMOS transistor is connected to a drain of the fourth NMOS transistor and to a second output;

a data write circuit comprising at least two NMOS transistors for receiving a pair of input signals; and

a data store circuit for storing data comprising at least two NMOS transistor,

wherein a pair of a drain of one of the two NMOS transistors in the data write circuit and a drain of one of the two NMOS transistors in the data store circuit is connected to the gate of the first NMOS transistor, and a pair of a drain of the other NMOS transistor in the data write circuit and a drain of the other NMOS transistors in the data store circuit is connected to the gate of the second NMOS transistor in the source follower circuit, respectively, and gates of the two NMOS transistors in the data store circuit are connected to the sources of the first NMOS transistor and the second NMOS transistor, respectively.

4. A flip flop circuit comprising:

a source follower circuit including

a first NMOS transistor and a second NMOS transistor;

a third NMOS transistor connected to a source of the first NMOS transistor,

an fourth NMOS transistor connected to a source of the second NMOS transistor; and

a current power source connected to both of the sources of the third NMOS transistor and the fourth NMOS transistor,

wherein both gates of the first NMOS transistor and the fourth NMOS transistor form a first input terminal to which a first input is provided, both gates of the second NMOS transistor and the third NMOS transistor form a second input terminal to which a second input whose level is obtained by inverting the level of the first input is provided, the source of the first NMOS transistor is connected to a drain of the third NMOS transistor and to a first output, and the source of the second NMOS transistor is connected to a drain of the fourth NMOS transistor and to a second output, and

wherein resistors are connected between the source of the third NMOS transistor and the current power source, and between the source of the fourth NMOS transistor and the current power source, respectively;

a data write circuit comprising at least two NMOS transistors; and

a data store circuit for storing data comprising at least two NMOS transistors,

wherein a pair of a drain of one of the two NMOS transistors in the data write circuit and a drain of one of the two NMOS transistors in the data store circuit is connected to the gate of the first NMOS transistor, and a pair of a drain of the other NMOS transistor in the data write circuit and a drain of the other NMOS transistors in the data store circuit is connected to the gate of the second NMOS transistor in the source follower circuit, respectively, and gates of the two NMOS transistors in the data store circuit are connected to the sources of the first NMOS transistor and the second NMOS transistor, respectively.