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Level conversion circuit controlled by clock signal

  • US 5,892,385 A
  • Filed: 11/15/1996
  • Issued: 04/06/1999
  • Est. Priority Date: 11/21/1995
  • Status: Expired due to Fees
First Claim
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1. A level conversion circuit receiving a clock signal to control timing, comprising:

  • a first circuit having a first clock input terminal, a signal input terminal and a first output node, wherein the first clock input terminal receives the clock signal, the signal input terminal receives a first input signal that alternates between a first power potential level and a reference potential level, and the first output terminal outputs a first output signal that changes between the first power potential level and the reference potential level, and wherein the first output node periodically reaches a high impedance state responsive to the clock signal;

    a second circuit coupled to the first output node for receiving the first output signal from the first circuit, the second circuit havinga second clock input terminal for receiving the clock signal;

    a second output node for outputting a second output signal that changes between a second power potential level and the reference potential level responsive to the first output signal, andan output circuit coupled to the second output node for outputting a converted output signal at said second output node that changes between the second power potential level and the reference potential level, wherein said converted circuit signal changes in response to a level of the first output signal and the clock signal; and

    a third circuit coupled to the first output node and the clock signal for setting the first output node at a first predetermined potential level when the first output node is in the high impedance state.

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