Method and apparatus for displaying grayscale data on a monochrome graphic display

• US 5,892,496 A
• Filed: 12/21/1995
• Issued: 04/06/1999
• Est. Priority Date: 12/21/1995
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Wakeland, Carl K.
• Primary Examiner(s): Nguyen, Chanh
• Assistant Examiner(s): SURACI, JOHN F
• Application Number:
  US08/576,107
• Time in Patent Office: 1,202 Days
• Field of Search: 345/147, 345/149, 345/150, 345/148, 345/153, 345/154, 345/132, 345/138, 345/112, 345/113, 358/534, 358/447, 358/536, 382/50
• US Class Current: 345/694
• CPC Class Codes: G09G 3/2018 by time modulation using two or more time intervals
• CPC Class Codes: G09G 3/2051 with use of a spatial dither pattern
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers

Abstract

A time-domain graphic synthesis method and apparatus form M single-bit patterns of length N to convert multiple-bit grayscale pixel data into single-bit binary display signals. M designates the number of gray levels to be displayed. N specifies a selected pattern size for usage in converting gray levels into perceived grayscale pixel data and advantages are gained if N is defined to be a prime number. Each of the N-bit binary patterns identifies a particular gray shade and each pattern, by definition, includes a plurality of ones and zeros. The ratio of the number of ones in an N-bit pattern to the total number N defines a relative intensity for that N-bit pattern. The relative intensity is indicative of and corresponds to the particular gray shade. The M single-bit patterns of length N are applied to a display which stores multiple-bit grayscale pixel data so that the column location of a pixel is converted to modulo-N form to designate one of the N bits of the pattern. Furthermore, for successive rows of the display, the column location of a pattern is progressively shifted or rotated with respect to a pixel. The shifting is modulo-N shifting and the amount of shifting is selected so that all N column locations are selected for N successive rows of the display. By applying the N-bit patterns in this manner, processing of all elements of the display includes processing of a matrix of adjacent N×N-bit squares. Processing of consecutive time frames of the display also includes shifting or rotating on a frame-by-frame basis, generating a repetitive pattern of N frames.

Claims

1. A display controller for converting multiple-bit grayscale pixels from a plurality of frames of a two-dimensional display into binary-valued pixels of a perceived grayscale display, the controller comprising:

a pattern generator generating M single-bit patterns of length N, M defining a number of different gray level values encoded by the multiple-bit grayscale pixels; and

an address generator coupled to the pattern generator and generating a modulo-N address addressing the generated patterns in combination with a gray level value applied from the two-dimensional display to designate a binary value for application to the perceived grayscale display, the modulo-N address being an additive combination, modulo-N, of a first dimension designator of the two-dimensional display, a second dimension designator of the two-dimensional display and a frame designator of the plurality of frames.

2. A display controller according to claim 1 wherein the address generator comprises:

a first counter counting units of the first dimension of the display;

a second counter counting units of the second dimension of the display;

a second counter offset incrementor coupled to the second counter and incrementing the second counter by a selected value; and

an adder coupled to the first counter and coupled to the second counter offset incrementor for adding the first counter units and the incremented second counter units.

3. A display controller according to claim 2 wherein the address generator further comprises:

a frame counter counting display frames; and

a frame counter offset incrementor coupled to the frame counter and incrementing the frame counter by a selected value;

wherein

the adder is further coupled to the frame counter offset incrementor for further adding the incremented frame count.

4. A display controller according to claim 1 wherein the pattern generator comprises:

a memory including an N×

M array having a plurality of gray level input lines coupled to the display, a plurality of address lines coupled to the address generator and a pixel data output line coupled to the perceived grayscale display.

5. A display controller according to claim 4 wherein the pattern generator N×

M array includes M single-bit patterns of length N having i ones and j zeros such that i/N is a relative intensity of a gray shade of the different gray level values.

6. A display controller according to claim 1, wherein the number, N, of single-bit patterns is an odd number.

7. A display controller according to claim 1, wherein the number, N, of single-bit patterns is a prime number.

8. A display controller according to claim 1, wherein the number, N, of single-bit patterns is 17 and a modulo-17 address generated by the address generator is an additive combination, modulo-17, of the first dimension designator and the second dimension designator shifted by four, modulo-17.

9. A display controller according to claim 1, wherein the number, N, of single-bit patterns is 19 and a modulo-19 address generated by the address generator is an additive combination, modulo-19, of the first dimension designator and the second dimension designator shifted by five, modulo-19.

11. A display controller according to claim 6, wherein:

the plurality of input lines to the row pattern shift memory is a first plurality of input lines; and

the row pattern shift memory has a second plurality of input lines coupled to the display supplying a gray level value.

10. A display controller for converting multiple-bit grayscale pixels from a plurality of frames of a two-dimensional display into binary-valued pixels of a perceived grayscale display, the controller comprising:

a pattern generator generating M single-bit patterns of length N, M defining a number of different gray level values encoded by the multiple-bit grayscale pixels; and

an address generator coupled to the pattern generator and generating a modulo-N address addressing the generated patterns in combination with a gray level value applied from the two-dimensional display to designate a binary value for application to the perceived grayscale display the modulo-N address being an additive combination modulo-N, of a first dimension designator of the two-dimensional display, a second dimension designator of the two-dimensional display and a frame designator of the plurality of frames, wherein the address generator includes;

a modulo-N column counter having an input terminal coupled to a column clock line, a reset terminal and a plurality of output lines;

a modulo-N row counter having an input terminal coupled to a row clock line, a reset terminal coupled to a vertical sync pulse line and a plurality of output lines;

a row pattern shift memory having a plurality of input lines coupled to the modulo-N row counter supplying a row shift value and having a plurality of output lines;

a spatial graphic modulo-N adder having a first plurality of input lines coupled to the modulo-N column counter, a second plurality of input lines coupled to the row pattern shift memory and having a plurality of output lines, the spatial graphic modulo-N adder for adding, modulo-N, a column count from the modulo-N column counter and a pattern-shifted row count from the row pattern shift memory;

a modulo-N frame counter having an input terminal coupled to the vertical sync pulse line, a reset line coupled to a system reset line and having a plurality of output lines;

a frame pattern shift memory having a first plurality of input lines coupled to the modulo-N frame counter supplying a frame shift value, having a second plurality of input lines coupled to the display supplying a gray level value and having a plurality of output lines; and

a frame modulo-N adder having a first plurality of input lines coupled to the spatial graphic modulo-N adder, a second plurality of input lines coupled to the frame pattern shift memory and having a plurality of output lines, the frame modulo-N adder for adding, modulo-N, the column count from the modulo-N column counter, the pattern-shifted row count from the row pattern shift memory and the pattern-shifted frame count from the frame pattern shift memory; and

the pattern generator includes a memory having an N×

M array having a plurality of gray level input lines coupled to the display, a plurality of address lines coupled to the frame modulo-N adder and a pixel data output line coupled to the perceived grayscale display.

12. A display controller according to claim 10, wherein the modulo-N column counter reset terminal is coupled to a row-clock line.

13. A display controller according to claim 10, wherein the modulo-N column counter reset terminal is coupled to a display-enable line.

15. A display controller according to claim 10, further comprising:

a frame shift encoder coupled between the gray level input lines and the frame pattern shift memory for encoding a gray level input signal so that the amount of pattern shifting is defined as a function of the applied gray level.

14. A display controller for converting multiple-bit grayscale pixels from a plurality of frames of a two-dimensional display into binary-valued pixels of a perceived grayscale display, the controller comprising:

a pattern generator generating M single-bit patterns of length N, M defining a number of different gray level values encoded by the multiple-bit grayscale pixels; and

an address generator coupled to the pattern generator and generating a modulo-N address addressing the generated patterns in combination with a gray level value applied from the two-dimensional display to designate a binary value for application to the perceived grayscale display, the modulo-N address being an additive combination, modulo-N, of a first dimension designator of the two-dimensional display, a second dimension designator of the two-dimensional display and a frame designator of the plurality of frames, wherein the address generator includes;

a modulo-N column counter having an input terminal coupled to a column clock line, a reset terminal coupled to a row clock line and a plurality of output lines;

a modulo-N row register having a input terminal coupled to a row clock line, a plurality of input lines, a reset terminal coupled to a vertical sync pulse line and a plurality of output lines;

a row pattern shift adder having a plurality of input lines coupled to the modulo-N row register supplying a row shift value and having a plurality of output lines coupled to the input lines of the modulo-N row register;

a spatial graphic modulo-N adder having a first plurality of input lines coupled to the output lines of the modulo-N column counter, a second plurality of input lines coupled to the output lines of the modulo-N row register and having a plurality of output lines, the spatial graphic modulo-N adder for adding, modulo-N, a column count from the modulo-N column counter and a pattern-shifted row count from the modulo-N row register;

a modulo-N frame counter having an input terminal coupled to the vertical sync pulse line, a reset line coupled to a system reset line and having a plurality of output lines;

a frame pattern shift memory having a first plurality of input lines coupled to the output lines of the modulo-N frame counter supplying a frame shift value, having a second plurality of input lines coupled to the display supplying a gray level value and having a plurality of output lines; and

a frame modulo-N adder having a first plurality of input lines coupled to the output terminal of the spatial graphic modulo-N adder, a second plurality of input lines coupled to the frame pattern shift memory and having a plurality of output lines, the frame modulo-N adder for adding, modulo-N, the column count from the modulo-N column counter, the pattern-shifted row count from the row pattern shift memory and the pattern-shifted frame count from the frame pattern shift memory; and

the pattern generator includes a memory having an N×

M array having a plurality of gray level input lines coupled to the display, a plurality of address lines coupled to the frame modulo-N adder and a pixel data output line coupled to the perceived grayscale display.

16. A method of converting multiple-bit grayscale pixel data from a plurality of frames of a two-dimensional display into binary-valued pixel data of a perceived grayscale display, the method comprising the steps of:

generating M single-bit patterns of length N, M defining a number of different gray level values encoded by the multiple-bit grayscale pixels and N being a prime number;

selecting a pattern of the generated M patterns and a bit of the selected pattern, the selecting step including the substeps of;

designating the pattern in accordance with a gray level value applied from the two-dimensional display to designate a binary value for application to the perceived grayscale display;

determining the bit of the selected pattern as an additive combination, modulo-N, of a first dimension designator of the two-dimensional display, a second dimension designator of the two-dimensional display and a frame designator of the plurality of frames.

17. A method according to claim 16 wherein the bit N determining step comprises the substeps of:

counting units of the first dimension of the display;

counting units of the second dimension of the display;

incrementing the second count by a selected value; and

adding the first counter units and the incremented second count units.

18. A method according to claim 17 wherein the bit N determining step further comprises the substeps of:

counting display frames;

incrementing the frame count by a selected value; and

adding the incremented frame count to the sum of the first count and the incremented second count.

19. A display system comprising:

a two-dimensional display having a plurality of multiple-bit grayscale pixels;

a two-dimensional perceived grayscale display having a plurality of binary-valued pixels;

a first dimension selector coupled to the display and the perceived grayscale display for addressing the display and the perceived grayscale display in a first dimension of the two dimensions;

a second dimension selector coupled to the display and the perceived grayscale display for addressing the display and the perceived grayscale display in a second dimension of the two dimensions;

a display controller coupled to the display and the perceived grayscale display for converting multiple-bit grayscale pixels from a plurality of frames of the display into binary-valued pixels of a perceived grayscale display, the display controller including;

a pattern generator generating M single-bit patterns of length N, M defining a number of different gray level values encoded by the multiple-bit grayscale pixels and N being a prime number; and

a pointer generator coupled to the pattern generator and generating a modulo-N pointer operating in combination with a gray level value applied from the two-dimensional display to designate a binary value for application to the perceived grayscale display, the modulo-N pointer being an additive combination, modulo-N, of a first dimension designator of the two dimensional display, a second dimension designator of the two-dimensional display and a frame designator of the plurality of frames.

20. A method of converting multiple-bit grayscale pixel data from a plurality of frames of a two-dimensional display into binary-valued pixel data of a two-dimensional perceived grayscale display, the method comprising the steps of:

segmenting the two-dimensional display into a plurality of adjacent square two-spatial dimensional square blocks having a selected first and second dimensional number of pixels;

organizing segmented display frames into a plurality of multiple-frame patterns in a time dimension;

designating an element of the organized and segmented display frames in the first dimension, second dimension and time dimension, the designated element having a location corresponding to the designation in the first and second dimensions of the two-dimensional display and the two-dimensional perceived grayscale display;

progressively shifting an element designation in the first dimension for successive element designations in the second dimension;

assigning a binary pixel value to an element according to position in the first dimension and according to multiple-bit gray scale value in the time dimension; and

displaying the assigned binary pixel value at the location of the perceived grayscale display corresponding to the first and second dimensional designations of the element.

21. A method according to claim 20 wherein the first and second dimensions of the two-spatial dimensional blocks have a prime number of pixels.

22. A method according to claim 20 wherein the time dimension of the multiple-frame pattern has a number of frames equal to the number of pixels in the first and second dimensions of the two-spatial dimensional blocks.

23. A method according to claim 20 wherein the first and second dimensions of the two-spatial dimensional blocks each have a length of 17 pixels element designations in the second dimension are progressively shifted four pixels modulo-17 for successive element designations in the second dimension.

24. A method according to claim 20 wherein the time dimension has a duration of 17 frames and the multiple-bit grayscale pixel data are defined by 16 gray levels.