Low noise amplifier for passive pixel CMOS imager

• US 5,892,540 A
• Filed: 06/13/1996
• Issued: 04/06/1999
• Est. Priority Date: 06/13/1996
• Status: Expired due to Fees

• Current Assignee: RE Secured Networks LLC
• Original Assignee: Rockwell International Corporation
• Inventors: Kozlowski, Lester J., Kleinhans, William A.
• Primary Examiner(s): Garber, Wendy
• Assistant Examiner(s): VU, NGOC YEN T
• Application Number:
  US08/662,382
• Time in Patent Office: 1,027 Days
• Field of Search: 330/86, 330/282, 330/308, 348/207, 348/222, 348/241, 348/243, 348/244, 348/245, 348/250, 348/294, 348/302, 348/303, 348/307, 348/308, 348/309, 348/310, 348/300, 348/301, 250/208.1
• US Class Current: 348/300
• CPC Class Codes: H04N 25/677 for reducing the column or line fixed pattern noise
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors

Abstract

A CMOS imaging system provides low noise read out and amplification for an array of passive pixels, each of which comprises a photodetector, an access MOSFET, and a second MOSFET that functions as a signal overflow shunt and a means for electrically injecting a test signal. The read out circuit for each column of pixels includes a high gain, wide bandwidth, CMOS differential amplifier, a reset switch and selectable feedback capacitors, selectable load capacitors, correlated double sampling and sample-and-hold circuits, an optional pipelining circuit, and an offset cancellation circuit connected to an output bus to suppress the input offset nonuniformity of the amplifier. For full process compatibility with standard silicided submicron CMOS and to maximize yield and minimize die cost, each photodiode may comprise the lightly doped source of its access MOSFET. Circuit complexity is restricted to the column buffers, which exploit signal processing capability inherent in CMOS. Advantages include high fabrication yield, broadband spectral response from near-UV to near-IR, low read noise at HDTV data rates, large charge-handling capacity, variable sensitivity with simple controls, and reduced power consumption.

Claims

1. A CMOS passive pixel sensor system, comprising:

a pixel comprising a photodetector connected to an access transistor;

a capacitive transimpedance amplifier (CTIA) having a CTIA input and a CTIA output;

an electrical bus connecting said pixel to said CTIA input;

a reset switch and a selectable feedback capacitance connected in parallel from said CTIA input to said CTIA output;

a selectable load capacitance connected to said CTIA output;

a first correlated double sampling circuit connected to said load capacitance;

a sample-and-hold buffer circuit connected to said first correlated double sampling circuit; and

an offset cancellation circuit connecting said buffer circuit to an output bus.

2. The CMOS passive pixel sensor system of claim 1, wherein said pixel further comprises an overflow transistor connected to said photodetector and having a gate continually biased for preventing saturation.

3. The CMOS passive pixel sensor system of claim 2, wherein said photodetector comprises a photodiode formed from a lightly doped source region of said access transistor.

4. The CMOS passive pixel sensor system of claim 1, wherein said capacitive transimpedance amplifier (CTIA) includes a high gain, wide bandwidth, CMOS differential amplifier.

5. The CMOS passive pixel sensor system of claim 4, wherein said CMOS differential amplifier has a first input connected to said CTIA input and a second input connected to a low noise reference.

6. The CMOS passive pixel sensor system of claim 5, wherein said second input of said CMOS differential amplifier is connected to a black pixel that generates said low noise reference for subtracting fixed pattern noise.

7. The CMOS passive pixel sensor system of claim 1, further comprising a pipeline circuit having at least first and second parallel paths connected between said buffer circuit and said offset cancellation circuit.

8. The CMOS passive pixel sensor system of claim 1, further comprising a second correlated double sampling circuit connected between said buffer circuit and said offset cancellation circuit.

9. The CMOS passive pixel sensor system of claim 8, wherein said offset cancellation circuit includes an output amplifier having an input connected to said second correlated double sampling circuit and an output connected to said output bus.

10. The CMOS passive pixel sensor system of claim 9, wherein said offset cancellation circuit further includes a low transconductance amplifier having an input connected to a low spatial noise reference signal and an output connected to said output bus.

11. A readout circuit for a CMOS passive pixel sensor system, comprising:

a plurality of pixels connected to an input bus, each of said pixels comprising a photodetector, an overflow transistor connected to said photodetector, and an access transistor connecting said photodetector to said input bus;

a high gain, wide bandwidth, CMOS differential amplifier having a first input connected to said input bus, a second input connected to a low noise reference, and an amplifier output;

a reset switch and a feedback capacitance connected in parallel from said input bus to said amplifier output;

a selectable load capacitance connected to said amplifier output;

a first correlated double sampling circuit connected to said load capacitance;

a sample-and-hold buffer circuit connected to said first correlated double sampling circuit;

an offset cancellation circuit connected to an output bus; and

a pipeline circuit having at least two parallel branches connecting said buffer circuit to said offset cancellation circuit.

12. The readout circuit of claim 11, wherein said feedback capacitance comprises a plurality of selectable feedback capacitors connected in parallel from said input bus to said amplifier output.

13. The readout circuit of claim 11, wherein each of said parallel branches of said pipeline circuit includes a second correlated double sampling circuit.

14. The readout circuit of claim 11, wherein said offset cancellation circuit comprises:

an output amplifier having an input connected to said pipeline circuit and an output connected to said output bus; and

a low transconductance amplifier having an input connected to a low spatial noise reference signal and an output connected to said output bus.

15. The readout circuit of claim 11, wherein said second input of said CMOS differential amplifier is connected to a black pixel that generates said low noise reference for subtracting fixed pattern noise.

16. A CMOS column readout circuit for an array of passive pixels, comprising:

a column bus connecting a column of said pixels to the readout circuit;

each of said column pixels comprising an access transistor connected to said column bus, a lightly doped source region of said access transistor forming a photodiode, and an overflow transistor connected to said photodiode;

a capacitive transimpedance amplifier (CTIA) comprising a high gain, wide bandwidth, CMOS differential amplifier having a first input connected to said column bus, a second input connected to a low noise reference, and an amplifier output;

said CTIA including a reset switch and a selectable feedback capacitance connected in parallel between said first amplifier input and said amplifier output;

a selectable load capacitance connected to said amplifier output;

a first correlated double sampling circuit connected to said load capacitance;

a sample-and-hold buffer circuit connected to said first correlated double sampling circuit;

an offset cancellation circuit connected to an output bus; and

a pipeline circuit having at least two parallel branches connecting said buffer circuit to said offset cancellation circuit, each of said parallel branches of said pipeline circuit includes a second correlated double sampling circuit.

17. The CMOS column readout circuit of claim 16, wherein said second input of said CMOS differential amplifier is connected to a black pixel that generates said low noise reference for subtracting fixed pattern noise.

18. The CMOS column readout circuit of claim 16, wherein said offset cancellation circuit includes an output amplifier having an input connected to said pipeline circuit and an output connected to said output bus.

19. The CMOS column readout circuit of claim 18, wherein said offset cancellation circuit further includes a low transconductance amplifier having an input connected to a low spatial noise reference and an output connected to said output bus.

20. The CMOS column readout circuit of claim 16, further comprising digital logic for reading out selected ones of said pixels connected to said column bus.