Imaging system and method for increasing the dynamic range of an array of active pixel sensor cells

• US 5,892,541 A
• Filed: 09/10/1996
• Issued: 04/06/1999
• Est. Priority Date: 09/10/1996
• Status: Expired due to Term

• Current Assignee: Foveon, Inc. (Avis Budget Group Incorporated)
• Original Assignee: Foveonics, Inc.
• Inventors: Merrill, Richard Billings
• Primary Examiner(s): Garber, Wendy
• Assistant Examiner(s): NGUYEN, LUONG TRUNG
• Application Number:
  US08/711,983
• Time in Patent Office: 938 Days
• Field of Search: 348/302, 348/304, 348/308, 348/297, 348/307, 348/301, 348/300, 348/296, 348/298, 348/312, 348/322, 348/164, 257/229, 257/230, 257/249
• US Class Current: 348/302
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H04N 25/533 by using differing integration times for different sensor regions
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Abstract

The dynamic range of an imaging system that utilizes an array of active pixel sensor cells is substantially increased by reading each cell in the array multiple times during each integration period. Each time a cell is read, the number of photons collected by the cell is saved and the cell is reset if the cell would normally saturate by the end of the integration period. At the end of the integration period, the number of photons collected by each cell is defined by the sum of the values collected during the integration period.

Claims

1. An imaging system comprising:

an array of active pixel sensor cells arranged in a number of rows and a number of columns;

a plurality of detection circuits corresponding to the number of columns;

an array controller and memory unit;

a plurality of row select lines connected to the array and the array controller and memory unit so that each row select line is connected to each of the cells in a row of active pixel sensor cells;

a plurality of row reset lines connected to the array and the array controller and memory unit so that each row reset line is connected to each of the cells in a row of active pixel sensor cells;

a plurality of column reset lines connected to the array and the array controller and memory unit so that each column reset line is connected to each of the cells in a column of active pixel sensor cells;

a plurality of cell output lines connected to the array and the detection circuits so that each cell output line is connected to each of the cells in a column of active pixel sensor cells and to a detection circuit that corresponds with the column of cells; and

a plurality of detection output lines connected to the detection circuits and the array controller and memory unit so that each detection output line is connected to a detection circuit.

2. The imaging system of claim 1 wherein each of the cells comprise:

a reset transistor connected to a power supply node, a first intermediate node, a row reset line, and a column reset line;

a photon collector connected to the first intermediate node;

a buffer transistor connected to the power supply node, a second intermediate node, and the first intermediate node; and

a row select transistor connected to the second intermediate node, a row select line, and a cell output line.

3. The imaging system of claim 2 wherein the reset transistor includes a split-gate transistor.

4. The imaging system of claim 2 wherein the photon collector includes a photodiode.

5. The imaging system of claim 1 wherein each detection circuit receives a cell output voltage from a cell output line, amplifies and digitizes the cell output voltage, and outputs the digitized output voltage on a detection circuit output line.

6. The imaging system of claim 1 wherein the array controller and memory unit selectively activates the column reset lines in response to information from the detection output lines.

7. An imaging system comprising:

a plurality of active pixel sensor cells arranged in rows and columns, each active pixel sensor cell collecting photons and converting the collected photons into a charge value;

a plurality of row select lines connected to the active pixel sensor cells so that each row select line is connected to each of the cells in a row of active pixel sensor cells, the row select lines conducting a row select signal;

a plurality of row reset lines connected to the active pixel sensor cells so that each row reset line is connected to each of the cells in a row of active pixel sensor cells, the row reset lines conducting a row reset signal;

a plurality of column reset lines connected to the active pixel sensor cells so that each column reset line is connected to each of the cells in a column of active pixel sensor cells, the column reset lines conducting a column reset signal;

an array controller and memory unit connected to the row select lines, the row reset lines, and the column reset lines that selectively activates the row reset lines and the column reset lines to reset the active pixel sensor cells which have a charge value that exceeds a predetermined limit.

8. The imaging system of claim 7 wherein each of the cells comprise:

a reset transistor connected to a power supply node, a first intermediate node, a row reset line, and a column reset line;

a photon collector connected to the first intermediate node;

a buffer transistor connected to the power supply node, a second intermediate node, and the first intermediate node; and

a row select transistor connected to the second intermediate node, a row select line, and a cell output line.

9. The imaging system of claim 8 wherein the reset transistor includes a split-gate transistor.

10. An imaging system comprising:

a plurality of active pixel sensor cells arranged in rows and columns, each active pixel sensor cell collecting photons and converting the collected photons into a charge value;

a plurality of row select lines connected to the active pixel sensor cells so that each row select line is connected to each of the cells in a row of active pixel sensor cells, the row select lines conducting a row select signal;

a plurality of row reset lines connected to the active pixel sensor cells so that each row reset line is connected to each of the cells in a row of active pixel sensor cells, the row reset lines conducting a row reset signal;

a plurality of column reset lines connected to the active pixel sensor cells so that each column reset line is connected to each of the cells in a column of active pixel sensor cells, the column reset lines conducting a column reset signal;

an array controller and memory unit connected to the row select lines, the row reset lines, and the column reset lines that determines the charge value on each cell a plurality of times during an integration period, stores the charge value each time the charge value exceeds a predetermined limit during the integration period, and resets the charge value each time the charge value is stored by selectively outputting the row reset and column reset signals on the row reset and column reset lines.

11. The imaging system of claim 10 wherein each of the cells comprise:

a reset transistor connected to a power supply node, a first intermediate node, a row reset line, and a column reset line;

a photon collector connected to the first intermediate node;

a buffer transistor connected to the power supply node, a second intermediate node, and the first intermediate node; and

a row select transistor connected to the second intermediate node, a row select line, and a cell output line.

12. The imaging system of claim 11 wherein the reset transistor includes a split-gate transistor.

13. The imaging system of claim 12 wherein, at the end of the integration period, the array controller and memory unit, for each active pixel sensor cell, stores the charge value to form a stored charge value, and combines the stored charge value with any charge value previously stored during the integration period.