Digital signal receiver circuit

• US 5,892,609 A
• Filed: 05/22/1997
• Issued: 04/06/1999
• Est. Priority Date: 05/24/1996
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Saruwatari, Eiji
• Primary Examiner(s): NEGASH, KINFE MICHAEL
• Application Number:
  US08/862,297
• Time in Patent Office: 684 Days
• Field of Search: 359/189, 250/214 A, 375/318, 330/59, 330/308
• US Class Current: 398/202
• CPC Class Codes: H04B 10/6933 Offset control of the differential preamplifier
• CPC Class Codes: H04B 10/695 Arrangements for optimizing the decision element in the receiver, e.g. by using automatic threshold control

Abstract

An optical signal is converted by a light-receiving element into a photoelectric current. The photoelectric current is converted by a preamplifier into a positive phase voltage and the opposite phase voltage. The peaks of the positive phase output and opposite phase output are sensed and held by a first and second peak sensing circuits. The median between the output of the second peak sensing circuit and the positive phase output of the preamplifier is determined by a first median output circuit. The median between the output of the first peak sensing circuit and the opposite phase output of the preamplifier is determined by a second median output circuit. A level comparison circuit compares the outputs of the first and second median output circuits and produces a signal voltage with a constant amplitude within a specific input voltage range, thereby producing a reception signal. This helps alleviate duty fluctuations and the deterioration of the reception sensitivity resulting from the dark current of the light-receiving element or fluctuations in the output offset voltage of the preamplifier.

Claims

1. A digital signal receiver circuit comprising:

a preamplifier for generating a positive phase signal and the opposite phase signal from an input digital signal;

a first level sensing circuit for sensing and holding either the peak value or the bottom value of the positive phase output of said preamplifier;

a second level sensing circuit for sensing and holding the same level value as that of said first level sensing circuit from the peak value or bottom value of the opposite phase output of said preamplifier;

a first median output circuit for outputting the median between the positive phase output of said preamplifier and the output of said second level sensing circuit;

a second median output circuit for outputting the median between the opposite phase output of said preamplifier and the output of said first level sensing circuit; and

a first level comparison circuit for comparing the output of said first median output circuit with the output of said second median output circuit and outputting a signal voltage with a constant amplitude within a specific input voltage range, wherein

said first and second level sensing circuits, first and second median output circuits, and said first level comparison circuit constitute an offset compensating section that performs the offset compensation of the DC level difference of the output of said preamplifier, and

said first level comparison circuit constitutes an amplitude limit amplifier section that compares and amplifies the output of said offset compensating section.

2. A digital signal receiver circuit according to claim 1, wherein said first and second median output circuits are each composed of resistance division circuits that divide and output both inputs in the resistance ratio.

3. A digital signal receiver circuit according to claim 1, wherein said first and second median output circuits are composed of a first and second adder circuits that add both inputs and output the result.

4. A digital signal receiver circuit according to claim 1, wherein said offset compensating section further includes reset means for resetting said first and second level sensing circuits.

5. A digital signal receiver circuit according to claim 4, wherein said reset means resets said first and second level sensing circuits with the timing of each input signal.

6. A digital signal receiver circuit according to claim 1, wherein more sets of said offset compensating section and amplitude limit amplifier section are repeated in the form of multistage connection.

7. A digital signal receiver circuit according to claim 1, further comprising:

a second level comparison circuit that has the gain half of the gain of said first level comparison circuit and that compares the output of said first level sensing circuit with the output of said second level sensing circuit and outputs a signal voltage with a constant amplitude within a specific input voltage amplitude range; and

a third adder circuit that adds the output of said first level comparison circuit to the output of said second level comparison circuit, wherein said second level comparison circuit and said third adder circuit constitute a DC level reproducing section that compensates for fluctuations in the outputs of said first and second level sensing circuits.

8. A digital signal receiver circuit according to claim 7, wherein said amplitude limit amplifier section and said DC level reproducing section include:

a first and second transistors that use the outputs of said first and second median output circuits as their base inputs, respectively;

a first and second emitter resistors which have the same resistance value and one end of each of which is connected to the emitter of each of said first and second transistors, respectively;

a first current source connected to the other end of each of said first and second emitter resistors;

a third and fourth transistors that use the outputs of said first and second level sensing circuits as their base inputs, respectively;

a third and fourth emitter resistors which have the resistance value twice that of said first and second emitter resistors and one end of each of which is connected to the emitter of each of said third and fourth transistors, respectively;

a second current source connected to the other end of each of said third and fourth emitter resistors;

a first collector resistor one end of which is connected to the collector of said first transistor and the collector of said third transistor and the other end of which is applied with a power supply voltage; and

a second collector resistor which has the same resistance value as that of said first collector resistor and one end of which is connected to the collector of said second transistor and the collector of said fourth transistor and the other end of which is applied with said power supply voltage, wherein

the collector combined output of said first and third transistors and the collector combined output of said second and fourth transistors are determined to be reception outputs.

9. A digital signal receiver circuit according to claim 7, wherein more sets of said offset compensating section, amplitude limit amplifier section, and DC level reproducing section are repeated in the form of multistage connection.

10. A digital signal receiver circuit according to claim 7, wherein said DC level reproducing section includes a differential circuit that has the same gain as that of said first or second median output circuit and that determines the difference between the outputs of said first and second level sensing circuits and outputs the positive phase signal and opposite phase signal, and

said second level comparison circuit has the same gain as that of said first level comparison circuit and compares the positive phase signal and opposite phase signal outputted from said differential circuit.

11. A digital signal receiver circuit according to claim 1, wherein said input digital signal is a photoelectric current produced by a light-receiving element.

12. A digital signal receiver circuit comprising:

a preamplifier for generating a positive phase signal and the opposite phase signal from an input digital signal;

a first level sensing circuit for sensing and holding either the peak value or the bottom value of the positive phase output of said preamplifier;

a second level sensing circuit for sensing and holding the same level value as that of said first level sensing circuit from the peak value or bottom value of the opposite phase output of said preamplifier;

a first differential circuit that determines the difference between the positive phase output of said preamplifier and the output of said first level sensing circuit and outputs the difference;

a second differential circuit that has the same gain as that of said first differential circuit and that determines the difference between the opposite phase output of said preamplifier and the output of said second level sensing circuit and outputs the difference;

a first level comparison circuit that compares the output of said first differential circuit with the output of said second differential circuit and outputs a signal voltage with a constant amplitude within a specific input voltage amplitude range;

a second level comparison circuit that has the gain equal to the product of the gain of said first or second differential circuit and the gain of said first level comparison circuit and that compares the output of said first level sensing circuit with the output of said second level sensing circuit and outputs a signal voltage with a constant amplitude within a specific input voltage amplitude range; and

an adder circuit that adds the output of said first level comparison circuit to the output of said second level comparison circuit, wherein

said first and second level sensing circuits, first and second differential circuits, and first level comparison circuit constitute an offset compensating section that performs the offset compensation of the DC level difference of the output of said preamplifier,

said first level comparison circuit constitutes an amplitude limit amplifier section that compares and amplifies the output of said offset compensating section, and

said second level comparison circuit and said adder circuit constitute a DC level reproducing section that compensates for fluctuations in the outputs of the first and second level sensing circuits.

13. A digital signal receiver circuit according to claim 12, wherein said offset compensating section further includes reset means for resetting said first and second level sensing circuits.

14. A digital signal receiver circuit according to claim 13, wherein said reset means resets said first and second level sensing circuits with the timing of each input signal.

15. A digital signal receiver circuit according to claim 12, wherein said amplitude limit amplifier section and said DC level reproducing section include:

a first and second transistors that use the outputs of said first and second differential circuits as their base inputs, respectively;

a first and second emitter resistors which have the same resistance value and one end of each of which is connected to the emitter of each of said first and second transistors, respectively;

a first current source connected to the other end of each of said first and second emitter resistors;

a third and fourth transistors that use the outputs of said first and second level sensing circuits as their base inputs, respectively;

a third and fourth emitter resistors which have the same resistance value as that of said first and second emitter resistors and one end of each of which is connected to the emitter of each of said third and fourth transistors, respectively;

a second current source connected to the other end of each of said third and fourth emitter resistors;

a first collector resistor one end of which is connected to the collector of said first transistor and the collector of said third transistor and the other end of which is applied with a power supply voltage; and

a second collector resistor which has the same resistance value as that of said first collector resistor and one end of which is connected to the collector of said second transistor and the collector of said fourth transistor and the other end of which is applied with said power supply voltage, wherein

the collector combined output of said first and third transistors and the collector combined output of said second and fourth transistors are determined to be reception outputs.

16. A digital signal receiver circuit according to claim 12, wherein said first and second differential circuits include:

a fifth and sixth transistors that use the positive phase output of said preamplifier and the output of said first level sensing circuit as their base inputs, respectively;

a fifth and sixth emitter resistors which have the same resistance value and one end of each of which is connected to the emitter of each of said fifth and sixth transistors, respectively;

a third current source connected to the other end of each of said fifth and sixth emitter resistors;

a seventh and eighth transistors that use the output of said second level sensing circuit and the opposite phase output of said preamplifier as their base inputs, respectively;

a seventh and eighth emitter resistors which have the same resistance value as that of said fifth and sixth emitter resistors and one end of each of which is connected to the emitter of each of said seventh and eighth transistors, respectively;

a fourth current source connected to the other end of each of said seventh and eighth emitter resistors;

a third collector resistor one end of which is connected to the collector of said fifth transistor and the collector of said seventh transistor and the other end of which is applied with a power supply voltage; and

a fourth collector resistor which has the same resistance value as that of said third collector resistor and one end of which is connected to the collector of said sixth transistor and the collector of said eighth transistor and the other end of which is applied with said power supply voltage, wherein

the collector combined output of said fifth and seventh transistors and the collector combined output of said sixth and eighth transistors are determined to be the outputs of said first and second differential circuits, respectively.

17. A digital signal receiver circuit according to claim 12, wherein more sets of said offset compensating section, amplitude limit amplifier section, and DC level reproducing section are repeated in the form of multistage connection.

18. A digital signal receiver circuit according to claim 12, wherein said DC level reproducing section includes a third differential circuit that has the same gain as that of said first or second differential circuit and that determines the difference between the outputs of said first and second level sensing circuits and outputs the positive phase signal and opposite phase signal, and

said second level comparison circuit has the same gain as that of said first level comparison circuit and compares the positive phase signal and opposite phase signal outputted from said third differential circuit.

19. A digital signal receiver circuit according to claim 12, wherein said input digital signal is a photoelectric current produced by a light-receiving element.

20. A digital signal receiver circuit comprising:

a preamplifier for generating a positive phase signal and the opposite phase signal from an input digital signal;

a first level sensing circuit for sensing and holding either the peak value or the bottom value of the positive phase output of said preamplifier;

a second level sensing circuit for sensing and holding the same level value as that of said first level sensing circuit from the peak value or bottom value of the opposite phase output of said preamplifier;

a first differential circuit that determines the difference between the positive phase output and opposite phase output of said preamplifier and outputs the difference;

a second differential circuit that has the same gain as that of said first differential circuit and that determines the difference between the outputs of said first and second level sensing circuits and outputs the difference;

a first level comparison circuit that compares the output of said first differential circuit with the output of said second differential circuit and outputs a signal voltage with a constant amplitude within a specific input voltage amplitude range;

a second level comparison circuit that has the gain equal to the product of the gain of said first or second differential circuit and the gain of said first level comparison circuit and that compares the output of said first level sensing circuit with the output of said second level sensing circuit and outputs a signal voltage with a constant amplitude within a specific input voltage amplitude range; and

an adder circuit that adds the output of said first level comparison circuit to the output of said second level comparison circuit, wherein

said first and second level sensing circuits, first and second differential circuits, and first level comparison circuit constitute an offset compensating section that performs the offset compensation of the DC level difference of the output of said preamplifier,

said first level comparison circuit constitutes an amplitude limit amplifier section that compares and amplifies the output of said offset compensating section, and

said second level comparison circuit and said adder circuit constitute a DC level reproducing section that compensates for fluctuations in the outputs of the first and second level sensing circuits.

21. A digital signal receiver circuit according to claim 20, wherein said offset compensating section further includes reset means for resetting said first and second level sensing circuits.

22. A digital signal receiver circuit according to claim 21, wherein said reset means resets said first and second level sensing circuits with the timing of each input signal.

23. A digital signal receiver circuit according to claim 20, wherein said amplitude limit amplifier section and said DC level reproducing section include:

a first and second transistors that use the outputs of said first and second differential circuits as their base inputs, respectively;

a first and second emitter resistors which have the same resistance value and one end of each of which is connected to the emitter of each of said first and second transistors, respectively;

a first current source connected to the other end of each of said first and second emitter resistors;

a third and fourth transistors that use the outputs of said first and second level sensing circuits as their base inputs, respectively;

a third and fourth emitter resistors which have the same resistance value as that of said first and second emitter resistors and one end of each of which is connected to the emitter of each of said third and fourth transistors, respectively;

a second current source connected to the other end of each of said third and fourth emitter resistors;

a first collector resistor one end of which is connected to the collector of said first transistor and the collector of said third transistor and the other end of which is applied with a power supply voltage; and

a second collector resistor which has the same resistance value as that of said first collector resistor and one end of which is connected to the collector of said second transistor and the collector of said fourth transistor and the other end of which is applied with said power supply voltage, wherein

the collector combined output of said first and third transistors and the collector combined output of said second and fourth transistors are determined to be reception outputs.

24. A digital signal receiver circuit according to claim 20, wherein said first and second differential circuits include:

a fifth and sixth transistors that use the positive phase output and opposite phase output of said preamplifier as their base inputs, respectively;

a fifth and sixth emitter resistors which have the same resistance value and one end of each of which is connected to the emitter of each of said fifth and sixth transistors, respectively;

a third current source connected to the other end of each of said fifth and sixth emitter resistors;

a seventh and eighth transistors that use the outputs of said first and second level sensing circuits as their base inputs, respectively;

a seventh and eighth emitter resistors which have the same resistance value as that of said fifth and sixth emitter resistors and one end of each of which is connected to the emitter of each of said seventh and eighth transistors, respectively;

a fourth current source connected to the other end of each of said seventh and eighth emitter resistors;

a third collector resistor one end of which is connected to the collector of said fifth transistor and the collector of said seventh transistor and the other end of which is applied with a power supply voltage; and

a fourth collector resistor which has the same resistance value as that of said third collector resistor and one end of which is connected to the collector of said sixth transistor and the collector of said eighth transistor and the other end of which is applied with said power supply voltage, wherein

the collector combined output of said fifth and seventh transistors and the collector combined output of said sixth and eighth transistors are determined to be the outputs of said first and second differential circuits, respectively.

25. A digital signal receiver circuit according to claim 20, wherein more sets of said offset compensating section, amplitude limit amplifier section, and DC level reproducing section are repeated in the form of multistage connection.

26. A digital signal receiver circuit according to claim 20, wherein said DC level reproducing section includes a third differential circuit that has the same gain as that of said first or second differential circuit and that determines the difference between the outputs of said first and second level sensing circuits and outputs the positive phase signal and opposite phase signal, and

said second level comparison circuit has the same gain as that of said first level comparison circuit and compares the positive phase signal and opposite phase signal outputted from said third differential circuit.

27. A digital signal receiver circuit according to claim 20, wherein said input digital signal is a photoelectric current produced by a light-receiving element.

28. A digital signal receiver circuit comprising:

a preamplifier for generating a positive phase signal and the opposite phase signal from an input digital signal;

a first level sensing circuit for sensing and holding either the peak value or the bottom value of the positive phase output of said preamplifier;

a second level sensing circuit for sensing and holding the same level value as that of said first level sensing circuit from the peak value or bottom value of the opposite phase output of said preamplifier;

a first differential circuit that determines the difference between the positive phase output and opposite phase output of said preamplifier and outputs at least the positive phase signal;

a second differential circuit that has the same gain as that of said first differential circuit and that determines the difference between the output of said first level sensing circuits and the output of said second level sensing circuit and outputs the positive phase signal and opposite phase signal;

a first level comparison circuit that compares the positive phase output of said first differential circuit with the positive phase output of said second differential circuit and outputs a signal voltage with a constant amplitude within a specific input voltage amplitude range;

a second level comparison circuit that has the same gain as that of said first level comparison circuit and that compares the positive phase output and opposite phase output of said second differential circuit and outputs a signal voltage with a constant amplitude within a specific input voltage amplitude range; and

an adder circuit that adds the output of said first level comparison circuit to the output of said second level comparison circuit, wherein

said first and second level sensing circuits and first and second differential circuits constitute an identification level sensing section that senses the identification level of the output of said first differential circuit,

said first level comparison circuit constitutes an amplitude limit amplifier section that compares and amplifies the output of said identification level sensing section, and

said second level comparison circuit and said adder circuit constitutes a DC level reproducing section that compensates for fluctuations in the outputs of the first and second level sensing circuits.

29. A digital signal receiver circuit according to claim 28, wherein said identification level sensing section further includes reset means for resetting said first and second level sensing circuits.

30. A digital signal receiver circuit according to claim 29, wherein said reset means resets said first and second level sensing circuits with the timing of each input signal.

31. A digital signal receiver circuit according to claim 28, wherein more sets of said identification level sensing section, amplitude limit amplifier section, and DC level reproducing section are repeated in the form of multistage connection.

32. A digital signal receiver circuit according to claim 28, wherein said DC level reproducing section includes a third differential circuit that has the same gain as that of said first or second differential circuit and that determines the difference between the outputs of said first and second level sensing circuits and outputs the positive phase signal and opposite phase signal, and

said second level comparison circuit has the same gain as that of said first level comparison circuit and compares the positive phase signal and opposite phase signal outputted from said third differential circuit.

33. A digital signal receiver circuit according to claim 28, wherein said input digital signal is a photoelectric current produced by a light-receiving element.