Fram, fram card, and card system using the same

• US 5,892,706 A
• Filed: 02/04/1998
• Issued: 04/06/1999
• Est. Priority Date: 08/29/1994
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation), Toshiba Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Tanaka, Sumio, Shimizu, Mitsuru
• Primary Examiner(s): Yoo, Do Hyun
• Application Number:
  US09/018,693
• Time in Patent Office: 426 Days
• Field of Search: 365/145, 365/65, 365/117, 365/149, 365/226
• US Class Current: 365/145
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels

Abstract

Circuitry within a ferroelectric memory prevents inversion of the polarization of ferroelectric memory cells caused by a power on reset signal to avoid corruption of data stored therein. A ferroelectric memory includes a memory cell array, a plurality of word lines commonly connected to the gates of the cell transistors in the same row, a plurality of plate lines commonly connected to the plates of the cell capacitors in the same row, a plurality of bit lines commonly connected to one end of the cell transistors in the same row, and a power on reset circuit for generating a power on reset signal of a predetermined level for a predetermined period of time after the power supply is turned on. An erroneous programming prevention circuit within the memory includes a plurality of switching transistors connected between all of the bit lines and plate lines and a plurality of nodes at a predetermined potential. The switching transistors are controlled by the power on reset signal so that they are on for a predetermined period of time.

Claims

1. A ferroelectric memory card comprising:

an LC filter for detecting an electromagnetic wave from a source external to the card;

a circuit for generating a signal from the electromagnetic wave detected by said LC filter;

a circuit for generating a power supply voltage from the electromagnetic wave detected by said LC filter;

a power on circuit for outputting a power on reset signal upon detection of said power supply voltage being at an operational level;

a memory cell array having a plurality of memory cells arranged in a matrix, each cell consisting of a capacitor having a ferroelectric material between electrodes thereof and a MOS transistor for transferring electrical charges, each MOS transistor within the memory cells belonging to a row being commonly connected by one word line, one of the electrodes of each capacitor within the memory cells belonging to a row being commonly connected by a plate line, one terminal of each MOS transistor of the memory cells belonging to a row being commonly connected by a bit line; and

a reset circuit for setting each of said plate lines and said word lines at a first potential in response to said power on reset signal.

2. A memory system constituted by a transmitter for transmitting program data which has been converted into an electromagnetic wave of a predetermined frequency and a ferroelectric memory card for receiving said electromagnetic wave to store said program data, said ferroelectric memory card comprising:

an LC filter for detecting the electromagnetic wave from a source external to the card;

a circuit for generating a signal from the electromagnetic wave detected by said LC filter;

a circuit for generating a power supply voltage from the electromagnetic wave detected by said LC filter;

a power on circuit for outputting a power on reset signal upon detection of said power supply voltage being at an operational level;

a memory cell array having a plurality of memory cells arranged in a matrix, each cell consisting of a capacitor having a ferroelectric material between electrodes thereof and a MOS transistor for transferring electrical charges, each MOS transistor within the memory cells belonging to a row being commonly connected by one word line, one of the electrodes of each capacitor within the memory cells belonging to a row being commonly connected by a plate line, one terminal of each MOS transistor of the memory cells belonging to a row being commonly connected by a bit line; and

a reset circuit for setting each of a plurality of plate lines and a plurality of word lines or a plurality of bit lines to a single potential in response to said power on reset signal.

3. A ferroelectric memory card comprising:

detector circuit for detecting an electromagnetic wave from a source external to the card;

a circuit for generating a signal from the electromagnetic wave detected by said detector circuit;

a power on circuit for outputting a power on reset signal upon detection of an operational power supply level;

a memory cell array having a plurality of memory cells arranged in a matrix, each cell consisting of a capacitor having a ferroelectric material between electrodes thereof and a MOS transistor for transferring electrical charges, each MOS transistor within the memory cells belonging to a row being commonly connected by one word line, one of the electrodes of each capacitor within the memory cells belonging to a row being commonly connected by a plate line, one terminal of each MOS transistor of the memory cells belonging to a row being commonly connected by a bit line; and

a reset circuit for setting each of a plurality of plate lines and a plurality of word lines or a plurality of bit lines to a single potential in response to said power on reset signal.

4. The ferroelectric memory card of claim 3 further comprising a circuit for generating a power supply voltage from the electromagnetic wave detected by said detector circuit.

5. A ferroelectric memory card comprising:

detector circuit for detecting an electromagnetic wave from a source external to the card;

a circuit for generating a signal from the electromagnetic wave detected by said detector circuit;

a power on circuit for outputting a signal indicative of the presence of an operational power supply level; and

a memory cell array having a plurality of memory cells arranged in a matrix, each cell consisting of a capacitor having a ferroelectric material between electrodes thereof and a MOS transistor for transferring electrical charges, each MOS transistor within the memory cells belonging to a row being commonly connected by one word line, one of the electrodes of each capacitor within the memory cells belonging to a row being commonly connected by a plate line, one terminal of each MOS transistor of the memory cells belonging to a row being commonly connected by a bit line.