Semiconductor non-volatile latch device including embedded non-volatile elements

• US 5,892,712 A
• Filed: 04/29/1997
• Issued: 04/06/1999
• Est. Priority Date: 05/01/1996
• Status: Expired due to Term

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG), NVX Corporation
• Original Assignee: NVX Corporation
• Inventors: Hirose, Ryan T., Lancaster, Loren T.
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US08/846,558
• Time in Patent Office: 707 Days
• Field of Search: 365/185.07, 365/154, 365/156, 365/189.05
• US Class Current: 365/185.07
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 14/0063 and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor

Abstract

A bistable non-volatile latch circuit adapted to store a non-volatile binary data state during a program operation, and to assume one of two stable states in response to a power up operation that correspond uniquely to the data state has first and second circuit sections. The first circuit section has a first non-volatile current path with means to set the impedance of the first current path in a non-volatile manner. A first end of the first current path is connected to provide a logic output signal, which represents a binary logic state depending on a voltage applied to the a first signal input node. The set/reset signal to the first current path varies between at least the power source voltage and a program voltage that is negative with respect to the power source voltage. A second circuit section generates an output voltage on a second output node that represents a binary logic state opposite from the output states of the first circuit section. Means are provided for connecting the first circuit section and the second circuit section into a bistable configuration.

Claims

1. A bistable non-volatile latch circuit adapted to store a non-volatile binary data state during a program operation, and to assume one of two stable states in response to a power up operation that correspond uniquely to said data state, comprising:

a first circuit section having a first node for receiving a logic input signal, a second node on which a logic output signal is generated, a third node for receiving a power source voltage, a fourth node to which a set/reset signal is supplied, a first non-volatile current path with means to set the impedance of said first current path in a non-volatile manner with a first end of said first current path connected to said second node and a first control node where said set/reset signal is supplied, and means for generating an output voltage on said second node that represents one binary logic state when a voltage is applied to said first node that represents the other binary logic state, where said set/reset signal varies between at least the power source voltage and a program voltage that is negative with respect to the power source reference potential; and

a second circuit section having a fifth node for receiving a logic input signal, a sixth node on which a logic output signal is generated, a seventh node for receiving a power source voltage, an eighth node for receiving a set/reset signal, a second non-volatile current path with means to set the impedance of said second current path in a non-volatile manner with a first end of said second current path connected to said sixth node and a second control node where said set/reset signal is supplied, and means of generating an output voltage on said sixth node that represents one binary logic state when a voltage is applied to said fifth node that represents the other binary logic state; and

means for connecting said first circuit section and said second circuit section into a bistable configuration.

2. The bistable non-volatile latch circuit of claim 1 wherein said means for connecting said first circuit section and said second circuit section into a bistable configuration comprises a permanent connection between said second and fifth nodes and a permanent low resistance connection between said sixth and first nodes.

3. The bistable non-volatile latch circuit of claim 1 wherein said means for connecting said first circuit section and said second circuit section into a bistable configuration comprises a permanent connection between a second end of said first non-volatile current path and said fifth node and a permanent connection between a second end of said second non-volatile current path and said first node.

4. The bistable non-volatile latch circuit of claim 1 wherein said first circuit section further comprises a first p-channel IGFET with a source node connected to said third node, a drain node connected to said second node and a gate connected to said first node, and further a second p-channel IGFET with a source node connected to said seventh node, a drain node connected to said sixth node and a gate connected to said fifth node.

5. The bistable non-volatile latch circuit of claim 1 wherein said first circuit section further comprises a first high impedance passive element with a first element end connected to said third node and a second element end connected to said second node, and further a second high impedance passive element with a first element end connected to said seventh node, a second element end connected to said sixth node.

6. The bistable non-volatile latch circuit of claim 1 wherein said first circuit section further comprises a first n-channel IGFET with a source node connected to said fourth node, a drain node connected to said second node and a gate connected to said first node, and further a second n-channel IGFET with a source node connected to said eighth node, a drain node connected to said sixth node and a gate connected to said fifth node.

7. The bistable non-volatile latch circuit of claim 4 wherein said first and second non-volatile current paths each comprises an n-channel IGFET non-volatile memory transistor comprised of at least a control gate, a non-volatile memory transistor source node, a non-volatile memory transistor drain node and a non-volatile memory transistor bulk node, a first end of said non-volatile current path comprising said non-volatile memory transistor drain and a second end of said non-volatile current path comprising said non-volatile memory transistor source, with means provided to permanently connect said non-volatile memory transistor source and said non-volatile memory transistor bulk nodes to said control node and means to permanently connect said control gate within said first non-volatile current path to said first end of said second current path and to permanently connect said control gate within said second non-volatile current path to said first end of said first current path.

8. The bistable non-volatile latch circuit of claim 6 wherein said first and second non-volatile current paths further each comprises an n-channel IGFET non-volatile memory transistor connected in series with a select transistor.

9. The bistable non-volatile latch circuit of claim 8 wherein said select transistor comprises an n-channel IGFET transistor with means to connect the source of said select transistor to the power source reference potential.

10. The bistable non-volatile latch circuit of claim 8 wherein said select transistor comprises an n-channel IGFET transistor with means to connect the source of said select transistor to said set/reset signal.

11. The bistable non-volatile latch circuit of claim 8 wherein said select transistor comprises an n-channel IGFET transistor with means to connect the source of said select transistor to a data input line.

12. The bistable non-volatile latch circuit of claim 8 wherein said select transistor comprises an p-channel IGFET transistor with means to connect the source of said select transistor to said power source voltage.

13. A method of transferring the contents of binary data stored in a bistable non-volatile latch circuit powered by a power supply voltage, and which further comprises a latch circuit and two n-channel non-volatile memory transistors with at least a bulk node and a gate node, comprising:

an erase operation wherein said bulk nodes are biased at the operating power supply voltage and said gate nodes are biased at a first negative potential with respect to the supply reference potential; and

a write operation wherein said bulk nodes and said gate nodes are biased at said supply reference potential and a storage bit is written to said latch circuit; and

a program operation wherein said storage bit is programmed into said non-volatile memory transistors by biasing said bulk nodes at a second negative potential with respect to said supply reference potential and said gate nodes at said operating power supply voltage; and

a set operation wherein at least said bulk nodes and said gate nodes are biased at said supply reference potential and the latch outputs produce potentials that represent the correct logic bit of the stored state.

14. The method of claim 13 wherein said set operation further comprises setting the power supply voltage equal to the power supply reference voltage and then subsequently setting the power supply voltage to said operating power supply voltage.

15. The method of claim 13 wherein said storage bit is the opposite binary data state of said correct logic bit.

16. The method of claim 13 wherein said storage bit is the same binary data state of said correct logic bit.

17. The method of claim 13 wherein said first negative potential is equal to said second negative potential.

18. A bistable non-volatile latch circuit adapted to store in a non-volatile fashion a binary data state at the time of a program operation, and to assume one of two stable states in response to a power up operation that correspond uniquely to said data state, said circuit comprising:

a first circuit section comprising a first node where a logic input signal is supplied, a second node where a logic output signal is generated, a third node where a power source voltage is applied, a fourth node where a reset/set signal is supplied, a first non-volatile current path with means to set the impedance of said first current path in a non-volatile manner with a first end of said first current path connected to said second node and a first control node where said reset/set signal is supplied, and means of generating an output voltage on said second node that represents one binary logic state when a voltage is applied to said first node that represents the other binary logic state, where said reset/set signal varies between at least the power source voltage and a program voltage that is negative with respect to the power source reference potential; and

a second circuit section comprising a fifth node where a logic input signal is supplied, a sixth node where a logic output signal is generated, a seventh node where a power source voltage is applied, a eighth node where a set/reset signal is supplied, a second non-volatile current path with means to set the impedance of said second current path in a non-volatile manner with a first end of said second current path connected to said sixth node and a second control node where said set/reset signal is supplied, and means of generating an output voltage on said sixth node that represents one binary logic state when a voltage is applied to said fifth node that represents the other binary logic state, where said set/reset signal varies between at least the power source voltage and a program voltage that is negative with respect to the power source reference potential; and

means for connecting said first circuit section and said second circuit section into a bistable configuration.

19. The bistable non-volatile latch circuit of claim 18 wherein said first circuit section further comprises a first p-channel IGFET with a source node connected to said third node, a drain node connected to said second node and a gate connected to said first node, and further a second p-channel IGFET with a source node connected to said seventh node, a drain node connected to said sixth node and a gate connected to said fifth node and said means for connecting said first circuit section and said second circuit section into a bistable configuration comprises a permanent connection between said second node and said fifth node and a permanent connection between said sixth node and said first node.